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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b972e14dc4dsm38046366b.36.2026.03.11.02.01.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Mar 2026 02:01:39 -0700 (PDT) Message-ID: Date: Wed, 11 Mar 2026 10:01:35 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/25] drm/msm/mdss: correct UBWC programming sequences To: Dmitry Baryshkov , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260311-ubwc-rework-v2-0-69f718f2a1c9@oss.qualcomm.com> <20260311-ubwc-rework-v2-1-69f718f2a1c9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260311-ubwc-rework-v2-1-69f718f2a1c9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=RYudyltv c=1 sm=1 tr=0 ts=69b12f76 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=ICUY2vpjD9Qnjj3NXwQA:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-GUID: t83OpUbTnhsns4E4KKrxCDioZolavdjf X-Proofpoint-ORIG-GUID: t83OpUbTnhsns4E4KKrxCDioZolavdjf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDA3NSBTYWx0ZWRfX3EmH2jQPQU72 JVPGF7LyZB2Znrcujd5WwdRUBRKMe+278aYTbFwmtY00v06nxr+741JNSie8V9XTbd23MJbiiiL WpOpSZTj9S3WOZVDJ4IsUbZGD1jOMkAvitcBRxTuyufRftZ5DiVfsgmHAlilPkzYLpTkpEMUK6h OjSulflqA9HtOku9L6kGugYkxcIE+GtsD9aiL0VmAvx5dNkUG2R8e+ZzPcmI2jnO2H8HQrYDgNd q3aSQQQxiZqGBokDc6xy8cozC1LZaiEDGuu8rbbpNo0bqZff6adlRrstz1RtvsVVtsX2/MwjJ3q WMSJoY26BKki5XB/zP5p6a6qTtw942/HMSr9PPRx2kAc0TYj0vvnthER16aej4y+2KUJa8YbsUp aECYWIw8sMV4UXubZVAvMQk5hnQTuU/m/wuT7owIHvBydXeNol8oHrSLgQfs8RjtwxD/jJ+Ix/E 9OkcK7Ro1HepPAObgKA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-11_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110075 On 3/11/26 4:22 AM, Dmitry Baryshkov wrote: > The UBWC registers in the MDSS region are not dependent on the UBWC > version (it is an invalid assumption we inherited from the vendor SDE > driver). Instead they are dependent only on the MDSS core revision. > > Rework UBWC programming to follow MDSS revision and to use required (aka > encoder) UBWC version instead of the ubwc_dec_version. > > Fixes: d68db6069a8e ("drm/msm/mdss: convert UBWC setup to use match data") > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/msm_mdss.c | 120 ++++++++++++++++------------------------- > 1 file changed, 45 insertions(+), 75 deletions(-) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 9047e8d9ee89..d8b0288f0040 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -166,27 +166,27 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) > return 0; > } > > -static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) > +static void msm_mdss_4x_setup_ubwc(struct msm_mdss *msm_mdss) > { > const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; > - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | > + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | > MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); > > - if (data->ubwc_bank_spread) > - value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; > - > if (data->ubwc_enc_version == UBWC_1_0) > value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); > > writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); > } > > -static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) > +static void msm_mdss_5x_setup_ubwc(struct msm_mdss *msm_mdss) > { > const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; > - u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | > + u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | > MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); > > + if (data->ubwc_bank_spread) > + value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; FWIW neither BANK_SPREAD nor the higher bits of UBWC_SWIZZLE exist on 8150 (MDP 5.0) or 8180 (MDP 5.1). They do on 8250 (MDP 6.0) [...] > + writel_relaxed(ver, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); > + writel_relaxed(prediction_mode, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); IDK if this is a concern, but this register has a note "Valid for UBWC_RGB565 only" Konrad