From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012005.outbound.protection.outlook.com [40.107.209.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2663356742 for ; Sun, 30 Aug 2026 23:18:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.5 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788131930; cv=fail; b=hXMiXoS5V6Rk7Wq3Azt670DUI2zZZ7vFqQKfWbL0bk7px9psIylmeVbyK1/iTGot+CiqYH+Q6tSvInjgwAaRHx2ea3tVCpTznfM/L5+eLy4+fNS716QmE9K4qLVBIfS7+acL6xzHlRvWK/+DE2WF87L9EhI592xolx3n6F4pn5w= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788131930; c=relaxed/simple; bh=oYg2rPQW4IqxSOUIYZONtrsAyZfddyOdP1coC33LMW8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lEj2o6fcfC5OrYOGOIYOSy9drIW0Cd1PWUcaXf7WB9UeVlRf9VMyKnKp/O6QcDvWWb36Yt5WM6m0YcgfGP/HSlflvW99bqSuqi1dG5v17BB/WCUYYNd1YVlD8Hh4PZnL4Sf6AAx4UA7JYcjlYN6slGSXJ82c/abjSQRs9jhL3iA= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=fKbgTBUq; arc=fail smtp.client-ip=40.107.209.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="fKbgTBUq" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CkjzfetgfecA4Q6S+BDztvdn1gxS8WYq2vjqU5+PhCrI4VN5oVcANQx/RYjF7t1zJZpr4jztaRGHyVst3ttwlSHZx+98eQ3iMZqaZXtxOHWvTemJAx8uq8B5AOCHI5vdu0d5PR/Yw87UZf8fCS4rDDMMTbxQ2No+ROJtaMOLTgArG/go5VgKVpoukOTOPRIH0Puv6xHMWBnX1SCbVXVSg3SFZthW//n/S87LA8aaKHhqdolE0SVlQjJZC+3aiO4JlHFEpXN0MUV0gyKLFac+H1Ao7YiFo9UuDEhoGBjoYyXvS+tEHqJ+Zqhz5//fex1CuxX0pH4kdGbuYK7yu7cXVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=65lU4TwOGwDXCbIGRmPhRTxCmE9Ugmh1tG7Y1eH/4/w=; b=rz2vZf3DEk9WONkyOCcKk8V8JKwV9Iy4Z8ocyA1zw8USBr6ZlnJYf2PcGRFH86OE7zgttf5eHWdyiFLDsDmBZXkZcPVPLpetpXtnj64ovUHNA2WjGiAnONHHH0eZXpocEJ7fuCUI2E++o2+9FdnQnA2EM/PhOL1abF5oMRl34jzLqBOaGuMISo84KZbIRDU+9xQMzf/nllLpDni3bgQ7tzEHRvxODSapxQTJqABc/aGuEW0F6LrByAnGzRKVgg4n9/nZ7d+LjX+MbjRVepogc1kasIt4d1kg7bLmuBP8x9tPjrWStyG7OX5t1/byRelnQA3+ndkb/+4qn4euFQkDTw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=65lU4TwOGwDXCbIGRmPhRTxCmE9Ugmh1tG7Y1eH/4/w=; b=fKbgTBUqcXIDHlGBjdMhePWtjF7FlakNn9E+zwRyAWzKQOvgqQ8XcAtKtDRueIsmF95nF872Y2KzY6KCHnTCyho2bawpsF7YQSMtChKH/JGUwjbMzK05cfsz/HBbLuvwLeiyWTV3NyxBSvRuQQnvJX5Y9gS/ypjo7iDI705GU3g98+zp3cCLh2xcVKgtEUdy5aMTZCrQZ6tCNriQpAQs6t6lq3FGZVkAXjhpKsZb47wlfGYxGvsl374qLIGJiJZsuISb/FF05aDlDSEsixs9oFPwmocrZPcZfUX6rxm4Cq3UHz3h0gj0ESiiBJveYFdW8UNurE/NapjORLolY3pIqQ== Received: from DS7P220CA0097.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:25a::6) by SJ2PR12MB9244.namprd12.prod.outlook.com (2603:10b6:a03:574::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.13; Sun, 30 Aug 2026 23:18:44 +0000 Received: from DS3PEPF0000C37D.namprd04.prod.outlook.com (2603:10b6:8:25a:cafe::28) by DS7P220CA0097.outlook.office365.com (2603:10b6:8:25a::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.360.13 via Frontend Transport; Sun, 30 Aug 2026 23:18:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF0000C37D.mail.protection.outlook.com (10.167.23.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.382.8 via Frontend Transport; Sun, 30 Aug 2026 23:18:44 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Sun, 30 Aug 2026 16:18:34 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Sun, 30 Aug 2026 16:18:33 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Sun, 30 Aug 2026 16:18:33 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v10 03/13] iommu/arm-smmu-v3: Add ARM_SMMU_FEAT_EVTQ for the event queue Date: Sun, 30 Aug 2026 16:18:04 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|SJ2PR12MB9244:EE_ X-MS-Office365-Filtering-Correlation-Id: 2bb61847-04b3-4155-55eb-08df06ed0963 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|82310400026|7416014|1800799024|376014|6133799003|56012099006|10067099003|5023799004|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: dsvrq7gFf5r3q7mqHloACE1lfru+qlqdl/DQ1jEkyKZGj64qpytJ8lUFc2jy8REbdjwP2alFmXR76o2qaqqL9ZQm7ufNngajIzcZ09qRk3zABujKYz2q7J/fUL+c61e54jU1rfmO/OGsKaHDKOfk/ossdcR+5iOY24FT+Uoj39GJKiu3pn2UqFv98rh6NvlABRqN/k9PKdHIh1rwrQPEbxIdmTv2pSUqYGWBSFROl2wLeYpBfd1QXWXuJhRoLFkg1PeKhuGgaHuRdUfUPvnU1cjozJW3k/DJKTgSDt5iucneTzP4/TQYiC+zRLfz87HsLHF168JTY0x9bvngYjQRzjotQSGDRsKSt77tBib9mCYIvP7lhmvIvPd+2w6ObpsD6XcTwowmzX9s+IQ8rO9N9t3nBsgPwKKxk5gfNYFxMY2rWmAVRV+dPcRmHpN2g8QnNdveO7B5IOxrz+nvRPNXNj5aGXPzchLXNE8CcYhgkKeMTuurJo4004vmDDD/fEL4UEyieGW+FIXZ+iWRPQJAb9EGG0WseJfM9F2ObLImamhZ6tXmn6YesFqAQ6WEj/qaV1ayqPPMeGbfNyCFyD9oMtpgIsg+xQwhF/LW23jXmgNLOjRr6sZs3XSV76u7r1zv/DJqq0xuTWe5EmE18XwZmxYAwlpvbUN7hGNP8pF43aM4wtulKL8O8+DM3ogWWg/3dobCZeoLyZAx0LmKgcV3Eg== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(82310400026)(7416014)(1800799024)(376014)(6133799003)(56012099006)(10067099003)(5023799004)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tTBuNoi/+y4ngwBjxQlfzOXz7HymzJcbhUosWCo/vupc7Zn98e2FNwYNw3HoOv56M11lvexZrUcygsBlc5im22z+AH1HBoRqdWbBIimyK9urOF/IPRG9TgKtZaEDdEfNwKbf9Mugz8uQ73jrSlv3Ym3KGjhwQoWogMSSMdWaeHY1OAIJgEaNNDQTU881ji6Cyc1NBYWglkRJ6zpNxkJ+wRZCMHcejgkojZCmnWO6Vm+iKAfnTYHbmfNySi+rfWL7jU45nG+i3zDHeQkKessvvTP0E+BqRYnAYaMbTgxzj7tuUVbC3hzpNoDVIFnM7Nu5BTi+LkaO7C94UrHIWtxMEZr+cDcYPMcHwduy8MTnYRzYYy5em87VlnY5rnLjn3Vzc8Xmw4MrgJ9P1IhinI8m91UTywIUr+XkrrBGDjph58ERzA9fKmuuvUTfp7dqgqzZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2026 23:18:44.3075 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bb61847-04b3-4155-55eb-08df06ed0963 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9244 The driver programs and enables the event queue unconditionally, while the PRI queue has an ARM_SMMU_FEAT_PRI gating each of its touch points. Yet a kdump kernel wants to leave both of the queues alone, which would take an is_kdump_kernel() test at every one of those places. Add an ARM_SMMU_FEAT_EVTQ that the probe always sets, as the event queue is architecturally mandatory, and gate the queue's allocation, its interrupt and its CR0 and IRQ_CTRL enables on it, so that a later change can turn the queue off in a single place. No functional change intended. Suggested-by: Jason Gunthorpe Suggested-by: Robin Murphy Assisted-by: Claude:claude-opus-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 79 +++++++++++++-------- 2 files changed, 52 insertions(+), 28 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index fd6f489cfedf2..75e768b3d66d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -927,6 +927,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_BBML2 (1 << 24) #define ARM_SMMU_FEAT_HAFT (1 << 25) #define ARM_SMMU_FEAT_DS (1 << 26) +#define ARM_SMMU_FEAT_EVTQ (1 << 27) u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c1d04f84870f6..c776fdd43325d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2349,7 +2349,8 @@ static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev) { struct arm_smmu_device *smmu = dev; - arm_smmu_evtq_thread(irq, dev); + if (smmu->features & ARM_SMMU_FEAT_EVTQ) + arm_smmu_evtq_thread(irq, dev); if (smmu->features & ARM_SMMU_FEAT_PRI) arm_smmu_priq_thread(irq, dev); @@ -2358,7 +2359,12 @@ static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev) static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) { - arm_smmu_gerror_handler(irq, dev); + struct arm_smmu_device *smmu = dev; + irqreturn_t ret = arm_smmu_gerror_handler(irq, dev); + + /* Without either queue, the thread would have nothing to drain */ + if (!(smmu->features & (ARM_SMMU_FEAT_EVTQ | ARM_SMMU_FEAT_PRI))) + return ret; return IRQ_WAKE_THREAD; } @@ -4505,11 +4511,14 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) return ret; /* evtq */ - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, - ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS, - EVTQ_ENT_DWORDS, "evtq"); - if (ret) - return ret; + if (smmu->features & ARM_SMMU_FEAT_EVTQ) { + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, + ARM_SMMU_EVTQ_PROD, + ARM_SMMU_EVTQ_CONS, + EVTQ_ENT_DWORDS, "evtq"); + if (ret) + return ret; + } if ((smmu->features & ARM_SMMU_FEAT_SVA) && (smmu->features & ARM_SMMU_FEAT_STALLS)) { @@ -4729,16 +4738,20 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) arm_smmu_setup_msis(smmu); /* Request interrupt lines */ - irq = smmu->evtq.q.irq; - if (irq) { - ret = devm_request_threaded_irq(smmu->dev, irq, NULL, - arm_smmu_evtq_thread, - IRQF_ONESHOT, - "arm-smmu-v3-evtq", smmu); - if (ret < 0) - dev_warn(smmu->dev, "failed to enable evtq irq\n"); - } else { - dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); + if (smmu->features & ARM_SMMU_FEAT_EVTQ) { + irq = smmu->evtq.q.irq; + if (irq) { + ret = devm_request_threaded_irq(smmu->dev, irq, NULL, + arm_smmu_evtq_thread, + IRQF_ONESHOT, + "arm-smmu-v3-evtq", smmu); + if (ret < 0) + dev_warn(smmu->dev, + "failed to enable evtq irq\n"); + } else { + dev_warn(smmu->dev, + "no evtq irq - events will not be reported!\n"); + } } irq = smmu->gerr_irq; @@ -4771,7 +4784,7 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) { int ret, irq; - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; + u32 irqen_flags = IRQ_CTRL_GERROR_IRQEN; /* Disable IRQs first */ ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, @@ -4797,6 +4810,8 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) } else arm_smmu_setup_unique_irqs(smmu); + if (smmu->features & ARM_SMMU_FEAT_EVTQ) + irqen_flags |= IRQ_CTRL_EVTQ_IRQEN; if (smmu->features & ARM_SMMU_FEAT_PRI) irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; @@ -4915,16 +4930,21 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) smmu, arm_smmu_make_cmd_op(CMDQ_OP_TLBI_NSNH_ALL)); /* Event queue */ - writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); - - enables |= CR0_EVTQEN; - ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, - ARM_SMMU_CR0ACK); - if (ret) { - dev_err(smmu->dev, "failed to enable event queue\n"); - return ret; + if (smmu->features & ARM_SMMU_FEAT_EVTQ) { + writeq_relaxed(smmu->evtq.q.q_base, + smmu->base + ARM_SMMU_EVTQ_BASE); + writel_relaxed(smmu->evtq.q.llq.prod, + smmu->page1 + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.llq.cons, + smmu->page1 + ARM_SMMU_EVTQ_CONS); + + enables |= CR0_EVTQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to enable event queue\n"); + return ret; + } } /* PRI queue */ @@ -5063,6 +5083,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) u32 reg; bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; + /* The event queue is architecturally mandatory, unlike the PRI queue */ + smmu->features |= ARM_SMMU_FEAT_EVTQ; + /* IDR0 */ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); -- 2.43.0