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Place the controller under a simple-bus with a 40-bit dma-ranges window so the DMA/IOMMU stack respects the interconnect address width when SMMU is enabled. The SoCDK daughter card only exposes the USB3.1 interface, so the unused USB0 (DWC2) board enablement is removed in a follow-up patch. This DTS series is posted separately from the USB bindings/driver series ("[PATCH v7 0/2] usb: dwc3: add Altera Agilex5 DWC3 support"). Depends on compatible "altr,agilex5-dwc3" from that series. --- changelog: v7->v8: * Rename simple-bus wrapper node from usb-bus@11000000 to bus@11000000 (Krzysztof Kozlowski). Use an approved simple-bus node name; do not invent usb-bus. v6->v7: * Split out of the USB series into a standalone DTS posting. Previous DTS series (v7): https://lore.kernel.org/all/cover.1789114403.git.adrian.ho.yin.ng@altera.com/ Previous combined series (v6): https://lore.kernel.org/all/cover.1788886615.git.adrian.ho.yin.ng@altera.com/ --- Adrian Ng Ho Yin (2): arm64: dts: intel: agilex5: add USB3.1 controller node arm64: dts: intel: agilex5: remove usb0 in Agilex5 SoCDK .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 4 +-- 2 files changed, 37 insertions(+), 2 deletions(-) base-commit: 93f51579e7df248780214094418f205253383cc5 -- 2.49.GIT