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DDR50 has no CMD19 tuning, so the read path must be centred by static, board/SoC-characterised PHY settings. Bringing it up on Agilex5 also exposed PHY issues affecting the existing tuned modes. - Patch 1: add the post-tuning settle delay the PHY needs after the DLL re-locks, matching sdhci_cdns6_phy_init(). - Patch 2: program PHONY_DQS_TIMING (left 0 in all modes); in extended-read DDR it must be the rebar pulse width in clk_phy cycles minus 1, else one DDR beat is duplicated. - Patch 3: document three optional SD6HC DDR50 read-path properties. - Patch 4: read those properties at probe and apply them in DDR50, and fix the DQS_TIMING read-modify-write so USE_LPBK_DQS is cleared before being reprogrammed. The new cdns,ddr50-* properties are unused in this series; they will be consumed by the socfpga_agilex5_socdk and socfpga_agilex5_socdk_emmc device trees, submitted as a separate series. Tested on Agilex5 SoCDK: SD DDR50 and eMMC DDR52. Tze Yee Ng (4): mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR dt-bindings: mmc: cdns,sdhci: add SD6HC DDR50 read-path tuning mmc: sdhci-cadence: read SD6HC DDR50 tuning from device tree .../devicetree/bindings/mmc/cdns,sd6hc.yaml | 27 ++++++ drivers/mmc/host/sdhci-cadence-phy-v6.c | 90 ++++++++++++++++++- 2 files changed, 116 insertions(+), 1 deletion(-) -- 2.43.7