Re: [PATCH 4/4] spi: cadence-qspi: Prevent SPI NAND continuous reads

[Santhosh Kumar K <s-k6@ti.com>]

Hello Mark and Miquel,

On 26/03/26 22:17, Miquel Raynal wrote:
> TI AM62Ax errata i2351, entitled "OSPI: Direct Access Controller (DAC)
> does not support Continuous Read mode with NAND Flash", explains that
> the CS can be deasserted almost at any time during a transfer (basically
> there is an interconnect arbitration every 1023 byte). This is an
> expected internal behaviour of the controller, but this leads to
> spurious CS deasserts. These are totally forbidden during SPI NAND
> continuous read transfers, because they indicate an end of transfer and
> the continuous read is then stopped on the flash side.
> 
> I initially tried to query the flash type and geometry to decide whether
> to apply a spi message size limit (there is a spi helper for that) but
> we cannot reliably get up to the MTD structure to discriminate if it is
> a NOR or a NAND we are playing with (it is not relevant to limit SPI NOR
> transfers, they are not affected). If we actually take this path, what
> limitation shall we enforce? The errata mentions 1023B, this is super
> low, less than a typical page size (about 2k or 4k, for most of them),
> so this is not usable. On my side, I only observed this problem on a
> 2-page read in octal DTR mode with more than 12 dummy cycles. The
> writesize summed with the oobsize could be a relevant boundary, but it
> is still quite arbitrary. Hence, I opted for implementing a controller
> capability flag, which then is used to decide whether the SPI NAND
> continuous read feature can be enabled.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

Just to confirm, has this patch not been picked up yet?

Regards,
Santhosh.

> ---
> I do not know if all flavours of this controller have the same
> limitation, or whether it is integration specific. As I only found
> mention of this errata for the AM62 processor, I opted for limiting the
> flag to a single compatible.
> ---
>   drivers/spi/spi-cadence-quadspi.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index 649ff55333f0..9f9b3013aa5d 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -1740,6 +1740,12 @@ static const struct spi_controller_mem_caps cqspi_mem_caps = {
>   	.per_op_freq = true,
>   };
>   
> +static const struct spi_controller_mem_caps cqspi_am654_mem_caps = {
> +	.dtr = true,
> +	.per_op_freq = true,
> +	.no_cs_assertion = true,
> +};
> +
>   static int cqspi_setup_flash(struct cqspi_st *cqspi)
>   {
>   	struct platform_device *pdev = cqspi->pdev;
> @@ -1797,6 +1803,8 @@ static int cqspi_probe(struct platform_device *pdev)
>   	host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;
>   	host->mem_ops = &cqspi_mem_ops;
>   	host->mem_caps = &cqspi_mem_caps;
> +	if (of_device_is_compatible(pdev->dev.of_node, "ti,am654-ospi"))
> +		host->mem_caps = &cqspi_am654_mem_caps;
>   
>   	cqspi = spi_controller_get_devdata(host);
>   	if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
>