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([2606:6d00:17:7b4b::5ac]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50337cbde30sm58435431cf.33.2026.01.30.06.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 06:47:36 -0800 (PST) Message-ID: Subject: Re: [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding From: Nicolas Dufresne To: ming.qian@oss.nxp.com, linux-media@vger.kernel.org Cc: mchehab@kernel.org, hverkuil-cisco@xs4all.nl, benjamin.gaignard@collabora.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, sebastian.fricke@collabora.com, shawnguo@kernel.org, ulf.hansson@linaro.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, l.stach@pengutronix.de, Frank.li@nxp.com, peng.fan@nxp.com, eagle.zhou@nxp.com, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Date: Fri, 30 Jan 2026 09:47:34 -0500 In-Reply-To: <20260130084133.2159-1-ming.qian@oss.nxp.com> References: <20260130084133.2159-1-ming.qian@oss.nxp.com> Autocrypt: addr=nicolas@ndufresne.ca; prefer-encrypt=mutual; keydata=mDMEaCN2ixYJKwYBBAHaRw8BAQdAM0EHepTful3JOIzcPv6ekHOenE1u0vDG1gdHFrChD /e0J05pY29sYXMgRHVmcmVzbmUgPG5pY29sYXNAbmR1ZnJlc25lLmNhPoicBBMWCgBEAhsDBQsJCA cCAiICBhUKCQgLAgQWAgMBAh4HAheABQkJZfd1FiEE7w1SgRXEw8IaBG8S2UGUUSlgcvQFAmibrjo CGQEACgkQ2UGUUSlgcvQlQwD/RjpU1SZYcKG6pnfnQ8ivgtTkGDRUJ8gP3fK7+XUjRNIA/iXfhXMN abIWxO2oCXKf3TdD7aQ4070KO6zSxIcxgNQFtDFOaWNvbGFzIER1ZnJlc25lIDxuaWNvbGFzLmR1Z nJlc25lQGNvbGxhYm9yYS5jb20+iJkEExYKAEECGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4 AWIQTvDVKBFcTDwhoEbxLZQZRRKWBy9AUCaCyyxgUJCWX3dQAKCRDZQZRRKWBy9ARJAP96pFmLffZ smBUpkyVBfFAf+zq6BJt769R0al3kHvUKdgD9G7KAHuioxD2v6SX7idpIazjzx8b8rfzwTWyOQWHC AAS0LU5pY29sYXMgRHVmcmVzbmUgPG5pY29sYXMuZHVmcmVzbmVAZ21haWwuY29tPoiZBBMWCgBBF iEE7w1SgRXEw8IaBG8S2UGUUSlgcvQFAmibrGYCGwMFCQll93UFCwkIBwICIgIGFQoJCAsCBBYCAw ECHgcCF4AACgkQ2UGUUSlgcvRObgD/YnQjfi4+L8f4fI7p1pPMTwRTcaRdy6aqkKEmKsCArzQBAK8 bRLv9QjuqsE6oQZra/RB4widZPvphs78H0P6NmpIJ Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-i/sogahe4R0AwUuBxOvE" User-Agent: Evolution 3.58.2 (3.58.2-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 --=-i/sogahe4R0AwUuBxOvE Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, Le vendredi 30 janvier 2026 =C3=A0 16:41 +0800, ming.qian@oss.nxp.com a =C3= =A9crit=C2=A0: > From: Ming Qian >=20 > The VPU G2 clock was reduced from 600MHz to 300MHz in commit > b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address > pixel errors with high-resolution HEVC postprocessor output. >=20 > However, testing shows the 300MHz clock rate is insufficient for > 4K60fps decoding and the original pixel errors no longer occur at > 600MHz with current drivers. Tested on EVK, with the downstream DCSS driver, and this change triggers DC= SS underrun (which is related to the DRAM QoS erratas on this SoC). It also sometimes trigger the "not all macroblock decoded" warning I added recently= , and we can empty IRQs, but these are handled now. >=20 > Test results with 3840x2160@60fps HEVC stream decoded to NV12 > (the same scenario that exhibited pixel errors previously): >=20 > 300MHz performance: > - Severe frame dropping throughout playback > - Only 336 frames rendered in 11:53 (0.471 fps) > - Continuous "A lot of buffers are being dropped" warnings > - Completely unusable for 4K video >=20 > 600MHz performance: > - Smooth playback with only 1 frame dropped at startup > - 37981 frames rendered in 10:34 (59.857 fps) > - Achieves target 60fps performance > - No pixel errors or artifacts observed That probably only true with the upstream DCSS + a small resolution embedde= d panel ? Can you clarify this setup, because the display drivers mainline ar= e very minimal. Would be nice to show you average DDR read/write bandwidth utilization during this run for comparision. Another information that bugs me, in the BSP code, the G2 voltage is increa= sed too, which you didn't do here. They also use the thermal 2 zone to kick it = down to 300 until it cools down. Nicolas >=20 > Restore the clock to 600MHz to enable proper 4K60fps decoding > capability while maintaining stability. >=20 > Test pipeline: > =C2=A0 gst-launch-1.0 filesrc location=3D<4K60_HEVC.mkv> ! \ > =C2=A0=C2=A0=C2=A0 video/x-matroska ! aiurdemux ! h265parse ! \ > =C2=A0=C2=A0=C2=A0 v4l2slh265dec ! video/x-raw,format=3DNV12 ! \ > =C2=A0=C2=A0=C2=A0 queue ! waylandsink >=20 > Fixes: b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") > Signed-off-by: Ming Qian > --- > =C2=A0arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- > =C2=A01 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 607962f807be..731142176625 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -960,7 +960,7 @@ pgc_vpu: power-domain@6 { > =C2=A0 =09 > <&clk IMX8MQ_SYS1_PLL_800M>, > =C2=A0 =09 > <&clk IMX8MQ_VPU_PLL>; > =C2=A0 assigned-clock-rates =3D > <600000000>, > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > <300000000>, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > <600000000>, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 > <800000000>, > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0>; > =C2=A0 }; >=20 > base-commit: c824345288d11e269ce41b36c105715bc2286050 > prerequisite-patch-id: 0000000000000000000000000000000000000000 --=-i/sogahe4R0AwUuBxOvE Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTvDVKBFcTDwhoEbxLZQZRRKWBy9AUCaXzEhgAKCRDZQZRRKWBy 9PeIAQD5M45/PuqurizwtvrI3NE0hSFwAP/bvFLOeVBaM9GzsQD+PGBAYJjzNYYA DPbDkSTiWXrcCwv7P2Bo3/hz5rdgBgU= =/XEy -----END PGP SIGNATURE----- --=-i/sogahe4R0AwUuBxOvE--