From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx1.white.stw.pengutronix.de (mx1.white.stw.pengutronix.de [185.203.200.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 468B03B995E; Mon, 31 Aug 2026 09:16:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.200.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788167802; cv=none; b=A2jqkF7Z75W2pNm4Z656xgZC2Z9+t6NtRhGn0c3CneyyvC81oK3LQmxOYh8OWm6Mwu1Z0EI6X2nn5Pi0CXJphKSu4V8xg/QsfMlMao5JMHbyq2Scxe54bpl6ZeQnbb9+gTrlft/ekQCYZfi2kc71U48G7VBUz8Yd6X5s6yF6evo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788167802; c=relaxed/simple; bh=+8KchVXGns7kDW3pqL6wMOIp6uEX4yhQz2r1emGVOyo=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=dNyoDqN1mv+9lBfo083xCGCWgYNPImCF2yeI5HDKOOmmthRWpTfdHMoy2UNCLOMJdTQ8lBhdkKxuzIMjp5p/PVOekYbGtFAll1z4lpqE1fPi/zXQg4636fx/1fkU2NnC7k4T3ZH5TKAIWIUlBRR7K8PcjW0J2p3LXuxTcy66RyE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.200.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from [IPv6:2a0a:edc0:0:900:1d::4e] (lupine.office.stw.pengutronix.de [IPv6:2a0a:edc0:0:900:1d::4e]) (Authenticated sender: pza@pengutronix.de) by mx1.white.stw.pengutronix.de (Postfix) with ESMTPSA id 1679A201EB9; Mon, 31 Aug 2026 11:16:37 +0200 (CEST) Message-ID: Subject: Re: [PATCH v3 07/13] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder From: Philipp Zabel To: Biju , Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Tommaso Merciai Date: Mon, 31 Aug 2026 11:16:37 +0200 In-Reply-To: <20260826174854.199139-8-biju.das.jz@bp.renesas.com> References: <20260826174854.199139-1-biju.das.jz@bp.renesas.com> <20260826174854.199139-8-biju.das.jz@bp.renesas.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Mi, 2026-08-26 at 18:48 +0100, Biju wrote: > From: Biju Das >=20 > Add support for the RZ/G3L LVDS encoder driver. It operates in single-lin= k > mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates > from 25 to 87 MHz. The LVDS module cannot be used at the same time as > MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock an= d > the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and > MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS > module. >=20 > Signed-off-by: Tommaso Merciai > Tested-by: Tommaso Merciai > Reviewed-by: Tommaso Merciai > Signed-off-by: Biju Das > --- [...] > --- > drivers/gpu/drm/renesas/rz-du/Kconfig | 13 + > drivers/gpu/drm/renesas/rz-du/Makefile | 1 + > drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c | 295 ++++++++++++++++++ > .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h | 25 ++ > 4 files changed, 334 insertions(+) > create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c > create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h >=20 [...] > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c b/drivers/gpu/drm= /renesas/rz-du/rzg3l_lvds.c > new file mode 100644 > index 000000000000..2a7ae67ff08d > --- /dev/null > +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c > @@ -0,0 +1,295 @@ [...] > +static int rzg3l_lvds_probe(struct platform_device *pdev) > +{ > + struct reset_control *rstc, *arstc; > + struct device *dev =3D &pdev->dev; > + struct rzg3l_lvds *lvds; > + void __iomem *base; > + int ret; > + > + lvds =3D devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge, > + &rzg3l_lvds_bridge_ops); > + if (IS_ERR(lvds)) > + return PTR_ERR(lvds); > + > + lvds->dev =3D dev; > + lvds->bridge.of_node =3D pdev->dev.of_node; > + > + base =3D devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + lvds->regmap =3D devm_regmap_init_mmio(dev, base, &rzg3l_lvds_regmap_co= nfig); > + if (IS_ERR(lvds->regmap)) > + return dev_err_probe(dev, PTR_ERR(lvds->regmap), > + "failed to init regmap\n"); > + > + lvds->dotclk =3D devm_clk_get(dev, "dotclk"); > + if (IS_ERR(lvds->dotclk)) > + return PTR_ERR(lvds->dotclk); > + > + rstc =3D devm_reset_control_get_exclusive(dev, "rst"); > + if (IS_ERR(rstc)) > + return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n"); > + > + arstc =3D devm_reset_control_get_exclusive(dev, "arst"); > + if (IS_ERR(arstc)) > + return dev_err_probe(dev, PTR_ERR(arstc), > + "failed to get arst\n"); It would be nice to have a comment about the two MIPI DSI resets having to be asserted here as well. Also, it looks like you could pair these two ... > + > + lvds->prstc =3D devm_reset_control_get_exclusive(dev, "prst"); > + if (IS_ERR(lvds->prstc)) > + return dev_err_probe(dev, PTR_ERR(lvds->prstc), > + "failed to get prst\n"); > + > + lvds->lvd_rstc =3D devm_reset_control_get_exclusive(dev, "lvdrst"); > + if (IS_ERR(lvds->lvd_rstc)) > + return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc), > + "failed to get core reset\n"); ... and these two into a devm_reset_control_bulk_get_exclusive() each. regards Philipp