RE: [PATCH v3] clk: Add support for fundamental zynq clks

[Michal Simek <michal.simek@xilinx.com>]

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> -----Original Message-----
> From: Mike Turquette [mailto:mturquette@ti.com]
> Sent: Wednesday, November 14, 2012 12:55 AM
> To: Josh Cartwright; Michal Simek
> Cc: Soren Brinkmann; Rob Herring; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; John Linn; arm@kernel.org
> Subject: Re: [PATCH v3] clk: Add support for fundamental zynq clks
> 
> Quoting Josh Cartwright (2012-11-13 15:26:48)
> > Provide simplified models for the necessary clocks on the zynq-7000
> > platform.  Currently, the PLLs, the CPU clock network, and the basic
> > peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
> >
> > OF bindings are also provided and documented.
> >
> > Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
> > ---
> > Michal-
> >
> > Here is a v3 with a fix for the problem Soren Brinkmann spotted.  Am I
> > correct that your current plan is to merge this into your tree?
> >
> > If so:
> >
> > Mike-
> >
> > Can we get your Acked-by on this one?
> >
> 
> Acked-by: Mike Turquette <mturquette@linaro.org>

Applied.

Thanks,
Michal




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