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Wed, 16 Sep 2026 07:28:49 -0700 (PDT) X-Received: by 2002:a05:690e:144f:b0:66c:bb59:e065 with SMTP id 956f58d0204a3-671631ddb2dmr912602d50.2.1789568929510; Wed, 16 Sep 2026 07:28:49 -0700 (PDT) Received: from [192.168.1.9] ([122.164.83.16]) by smtp.gmail.com with ESMTPSA id 00721157ae682-891f0b96dc4sm8668607b3.36.2026.09.16.07.28.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Sep 2026 07:28:49 -0700 (PDT) Message-ID: Date: Wed, 16 Sep 2026 19:58:40 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: gcc-ipq5424: Fix TME reset register offsets To: Abel Vesa , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Sricharan Ramabadhran , Varadarajan Narayanan , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260916-clk-qcom-gcc-ipq5424-fix-tme-bcrs-offsets-v1-1-0fa10674908a@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20260916-clk-qcom-gcc-ipq5424-fix-tme-bcrs-offsets-v1-1-0fa10674908a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE2MDE5NCBTYWx0ZWRfX6fwXvHBR4m1n eIRCkcYReXsE9r2L9XBJ7T6zuP3EGRbaLioanaSA8RGSl+jB9PFTBb4H7jKJ9z3NoX5LOuTrb9O 6Q/uMttpDeBM5+t/B4/H0rgav8MY9x0= X-Proofpoint-GUID: 7MrJEAfY7cEsU3Nbaj5YHCPwRbcUg0tb X-Authority-Analysis: v=2.4 cv=N4m8hG9B c=1 sm=1 tr=0 ts=6aaaa7a2 cx=c_pps a=S/uc88zpIJVNbziUnJ6G4Q==:117 a=OZlrBAJz/5WJp+wn98y/tA==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=1YwTZjUziwFERy13GwQA:9 a=QEXdDO2ut3YA:10 a=nd2WpGr1bMy9NW-iytEl:22 X-Proofpoint-ORIG-GUID: 7MrJEAfY7cEsU3Nbaj5YHCPwRbcUg0tb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE2MDE5NCBTYWx0ZWRfX87uLL11epNbR GKds3SEgxJ0cAlbmDJH9XzDgVfYbQ/uA7X+9r3c5CQa1bnq8BdKqvpLk552ovSZjQXrxK2GvxmN OLfdcjFEC+AlyK0RCgB/cqxv4UEtIXm8Ls2EZ5Ucv44NMv0pFRRUIkwy51e62y3LCBZhPhKYitW l1Ce124wbzCYy2+3ABgAA5oP0kW7IUqx3ffqXA22dumgS1gXCFHXyLIek2jo3Z+Ar0U7wEMkVWK JuEmAnrby6hkFQhg3ZjoXVFl1J3WcgOpP8cx6DdQ/6Eq0aNYIulw+5ytTn56wIdjVT2/8W+2byi kRR0DBTNrZtkEAIbA9LyjxTzRsxC56rHFTUlFSNJx5YMezKoucBxoomEnNk6eVvGm24Fwqlz3W8 aGawihoZjEvqIxEfGSCGXGiDKj0x1+gordeKb0aaUHPzQxj5NE4pbr9SpLFoULWuTWCBr7Xnrwq pABKgD6nt3eGpdhn91A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-16_02,2026-09-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609160194 On 9/16/2026 4:59 PM, Abel Vesa wrote: > The GCC_TME_BCR and GCC_TME_SEC_BUS_BCR offsets exceed the regmap maximum > of 0x3f024. Regmap therefore rejects accesses to both registers, leaving > the resets ineffective while the reset operations report success. > > The offsets appear to contain typographical errors. Use 0x10000 for > GCC_TME_BCR, matching the offset used on IPQ9574 and the surrounding > register layout. Use 0x1a030 for GCC_TME_SEC_BUS_BCR, placing it in the > same register block as GCC_SEC_CTRL_BCR at 0x1a000. > > Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC") > Assisted-by: LLM > Signed-off-by: Abel Vesa > --- > The replacement offsets are inferred from the register layout and the > IPQ9574 driver; > > Sricharan, could you please confirm both offsets, particularly 0x1a030 > for GCC_TME_SEC_BUS_BCR? Abel, I confirm that both offsets are correct and matching with HW doc. So, Reviewed-by: Kathiravan Thirumoorthy