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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 1tk0VhFHLLIRxLSK1OCmzL9OpMYkm0ut X-Authority-Analysis: v=2.4 cv=XK0AjwhE c=1 sm=1 tr=0 ts=6a200188 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=AMbOtgs2x-SaA9YGKiUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAzMDEwMCBTYWx0ZWRfX+0mkMxz2r3T4 i1biBxkSNW9642g/x/KJum0EyrkG4/nlGGz32NjncT+geUL03ijzzOLkBIlBI+EAOAK2gpi4WH5 oq7A5rXWAAIy4lpPd0W2joqRZb+bWIqXj0PDqUrE6Djym/u/wbQwYHXWcvCTjgF/4RwT/FwSIyr 7YxlzAhPHP3h65FmO2mg+KaqE0QbflUZbiBd4wbDrLCvLvUME8mK9T47ayVQfcJ69eyVuIv7tSk 46dFMm4I0KQdvCTSQVzCl6vfwHV62HtawECXD7l1pLDqlfbIIBjN1ZtXj/6V64sfUwne10Yca4q rHyqa7TYUBvGsQcB+JF7Z0+7Y6A3x0uH3+iLxig1ELqyScBJQ1OYYZ2nH3iIAUkrpuK8oMRzF4p AK941COswES+NbGysAb96BPXqM6H+v+j5iKydpSJB8t2xKMWLEjOgSVRh2Nz8/E4adRGIhzGVbe B0x4BLazRV7uC1FlYjg== X-Proofpoint-ORIG-GUID: 1tk0VhFHLLIRxLSK1OCmzL9OpMYkm0ut X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-03_03,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606030100 Hello Rob, On 5/20/2026 11:43 PM, Umang Chheda wrote: > Hello Rob, > > Thanks for helping reviewing the code! > > On 5/13/2026 11:28 PM, Rob Herring wrote: >> On Tue, May 05, 2026 at 05:53:49PM +0530, Umang Chheda wrote: >>> The Arm Error Source Table (AEST) specification describes how firmware >>> exposes RAS error source topology to the operating system. On ACPI >>> systems this information is provided via the AEST ACPI table. >>> >>> Introduce Device Tree bindings that provide an equivalent description >>> of AEST error sources for DT-based platforms. >>> >>> Signed-off-by: Umang Chheda >>> --- >>> .../devicetree/bindings/arm/arm,aest.yaml | 406 +++++++++++++++++++++ >>> include/dt-bindings/arm/aest.h | 43 +++ >>> 2 files changed, 449 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/arm,aest.yaml b/Documentation/devicetree/bindings/arm/arm,aest.yaml >>> new file mode 100644 >>> index 000000000000..7809a0d38270 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/arm,aest.yaml >>> @@ -0,0 +1,406 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/arm/arm,aest.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Arm Error Source Table (AEST) >>> + >>> +maintainers: >>> + - Umang Chheda >>> + >>> +description: >>> + The Arm Error Source Table (AEST) describes RAS error sources and their >>> + register interfaces. Each error source exposes one or more error records >>> + through either system registers or a memory-mapped register window, and >>> + may signal errors via interrupts. The top-level node acts as a container >>> + for one or more child nodes, each describing a single AEST error source. >>> + Refer to the Arm AEST specification (DEN0085 / DDI 0587B) for details. >>> + Flag bit constants for use in DT source files are defined in >>> + . >>> + >>> +properties: >>> + compatible: >>> + const: arm,aest >>> + >>> + "#address-cells": >>> + const: 2 >>> + >>> + "#size-cells": >>> + const: 2 >>> + >>> + ranges: true >>> + >>> +required: >>> + - compatible >>> + >>> +additionalProperties: false >>> + >>> +patternProperties: >>> + "^aest-[a-z0-9-]+(@[0-9a-f]+)?$": >>> + type: object >>> + description: >>> + An AEST error source node describing one error source defined by >>> + the Arm AEST specification. >>> + >>> + properties: >>> + compatible: >>> + description: >>> + Identifies the type of AEST error source. Each value corresponds to >>> + a distinct error source class defined by the Arm AEST specification. >>> + arm,aest-proxy represents a proxy error source that forwards errors >>> + from another error source. >>> + enum: >>> + - arm,aest-processor >>> + - arm,aest-memory >>> + - arm,aest-smmu >>> + - arm,aest-gic >>> + - arm,aest-pcie >>> + - arm,aest-vendor >>> + - arm,aest-proxy >> >> This is a fundamental difference how DT and ACPI get structured. ACPI >> defines new table for some feature and puts everything in that table. >> For DT, these all belong in the node for the corresponding h/w. For >> example, if the GIC supports AEST, then that belongs in the GIC node. > > Thanks for the feedback. To clarify your suggestion — should the AEST > RAS properties be added directly as properties of the hardware node > (e.g. arm,ras-num-records inside the cpu@0 node itself), or as a child > node under the hardware node (e.g. a ras-error-source {} child under cpu@0)? Can you please help with this query ? > > >> >>> + >>> + reg: >>> + description: >>> + Register ranges for the error source. Absence of reg implies >>> + system-register access (interface type 0). A single range implies >>> + memory-mapped access (interface type 1). Two ranges imply >>> + single-record memory-mapped access (interface type 2). >>> + minItems: 1 >>> + maxItems: 4 >>> + >>> + reg-names: >>> + description: >>> + Names for the register ranges. The base error-record window is >>> + unnamed (or first entry). Optional named ranges provide access to >>> + the fault-injection, error-group, and interrupt-config register >>> + windows defined by the AEST specification. >>> + minItems: 1 >>> + maxItems: 4 >>> + items: >>> + enum: >>> + - fault-inject >>> + - err-group >>> + - irq-config >>> + >>> + interrupts: >>> + description: Interrupts associated with the error source. >>> + minItems: 1 >>> + maxItems: 2 >>> + >>> + interrupt-names: >>> + description: Names of the interrupts associated with the error source. >>> + minItems: 1 >>> + maxItems: 2 >>> + items: >>> + enum: >>> + - fhi >>> + - eri >>> + >>> + arm,fhi-flags: >>> + description: >>> + Bitmask of flags for the fault-handling interrupt (FHI), as defined >>> + in the AEST node interrupt structure flags field. Constants are >>> + defined in - AEST_IRQ_MODE_LEVEL (0), >>> + AEST_IRQ_MODE_EDGE (1). >> >> DT already has a way to define interrupt flags. Why invent something >> new? > > Ack, this flag is not needed for DT based systems, will remove this. > >> >> Rob > > Thanks, > Umang > > Thanks, Umang