From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
To: Sunny Luo <sunny.luo@amlogic.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Xianwei Zhao <xianwei.zhao@amlogic.com>
Subject: [PATCH v3 2/4] spi: amlogic: spisg: Fix transfer size limit and timeout handling
Date: Fri, 31 Jul 2026 09:08:26 +0000 [thread overview]
Message-ID: <20260731-a9-spisg-v3-2-a15da3f70029@amlogic.com> (raw)
In-Reply-To: <20260731-a9-spisg-v3-0-a15da3f70029@amlogic.com>
From: Xianwei Zhao <xianwei.zhao@amlogic.com>
The CFG_BLOCK_NUM field can encode at most 20 bits, so reduce
SPISG_BLOCK_MAX to 0xfffff to avoid programming a zero-length transfer.
Perform the delay calculation in 64-bit arithmetic to avoid overflow
when converting nanoseconds to SPI clock cycles.
Stop the controller on transfer timeout by clearing the descriptor list
register before returning an error.
Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
drivers/spi/spi-amlogic-spisg.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spisg.c
index afc8af04638d..a6123975a37c 100644
--- a/drivers/spi/spi-amlogic-spisg.c
+++ b/drivers/spi/spi-amlogic-spisg.c
@@ -95,7 +95,7 @@
#define SPISG_MAX_REG 0x40
-#define SPISG_BLOCK_MAX 0x100000
+#define SPISG_BLOCK_MAX 0xFFFFF
#define SPISG_OP_MODE_WRITE_CMD 0
#define SPISG_OP_MODE_READ_STS 1
@@ -175,7 +175,7 @@ static int spi_delay_to_sclk(u32 slck_speed_hz, struct spi_delay *delay)
if (ns < 0)
return 0;
- return DIV_ROUND_UP_ULL(slck_speed_hz * ns, NSEC_PER_SEC);
+ return DIV_ROUND_UP_ULL((u64)slck_speed_hz * ns, NSEC_PER_SEC);
}
static inline u32 aml_spisg_sem_down_read(struct spisg_device *spisg)
@@ -565,10 +565,13 @@ static int aml_spisg_transfer_one_message(struct spi_controller *ctlr,
aml_spisg_pending(spisg, descs_paddr, false, true);
if (wait_for_completion_timeout(&spisg->completion,
spi_controller_is_target(spisg->controller) ?
- MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms)))
+ MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) {
ret = spisg->status ? -EIO : 0;
- else
+ } else {
+ /* stop transfer */
+ regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, 0);
ret = -ETIMEDOUT;
+ }
dma_unmap_single(dev, descs_paddr, descs_len, DMA_TO_DEVICE);
end:
--
2.52.0
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next prev parent reply other threads:[~2026-07-31 9:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-31 9:08 [PATCH v3 0/4] spi: add support for Amlogic A9 Xianwei Zhao via B4 Relay
2026-07-31 9:08 ` [PATCH v3 1/4] spi: dt-bindings: amlogic: spisg: Document A9-specific properties Xianwei Zhao via B4 Relay
2026-07-31 22:51 ` Mark Brown
2026-08-03 9:13 ` Xianwei Zhao
2026-07-31 9:08 ` Xianwei Zhao via B4 Relay [this message]
2026-07-31 9:22 ` [PATCH v3 2/4] spi: amlogic: spisg: Fix transfer size limit and timeout handling sashiko-bot
2026-07-31 9:08 ` [PATCH v3 3/4] spi: amlogic: spisg: Fix the incorrect keep_ss of the last descriptor Xianwei Zhao via B4 Relay
2026-07-31 9:20 ` sashiko-bot
2026-07-31 9:08 ` [PATCH v3 4/4] spi: amlogic: spisg: Add support for A9 controller features Xianwei Zhao via B4 Relay
2026-07-31 9:19 ` sashiko-bot
2026-09-04 17:06 ` [PATCH v3 0/4] spi: add support for Amlogic A9 Mark Brown
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