From: Hans Zhang <18255117159@163.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, jingoohan1@gmail.com, mx@lists.linux.dev,
linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev,
linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] PCI: dwc: Cache PCIe capability offset and simplify drivers
Date: Wed, 20 May 2026 00:52:49 +0800 [thread overview]
Message-ID: <e0c89a4a-709e-42c6-ad1c-7ec50cc5790c@163.com> (raw)
In-Reply-To: <m332ocvmmdzcgnzmzxmbn2nmczxuhplt5efh64fd22fagrot42@x3okixj5qjb2>
On 5/20/26 00:49, Manivannan Sadhasivam wrote:
> On Wed, May 20, 2026 at 12:27:21AM +0800, Hans Zhang wrote:
>>
>>
>> On 5/20/26 00:15, Manivannan Sadhasivam wrote:
>>> On Wed, May 20, 2026 at 12:09:28AM +0800, Hans Zhang wrote:
>>>>
>>>>
>>>> On 5/19/26 21:57, Manivannan Sadhasivam wrote:
>>>>> On Sat, May 09, 2026 at 09:51:49PM +0800, Hans Zhang wrote:
>>>>>> The DWC PCIe core and its many platform drivers repeatedly call
>>>>>> dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) to obtain the offset of the
>>>>>> PCI Express Capability structure. This is wasteful and makes the code
>>>>>> verbose. And some even search for the PCI_CAP_ID_EXP offset value within
>>>>>> the suspend/resume functions.
>>>>>>
>>>>>
>>>>> Sashiko has flagged some real issues with this series in accessing DBI space
>>>>> very early and 'pci->pcie_cap' being 0.
>>>>
>>>>
>>>> Hi Mani,
>>>>
>>>> We have discussed this issue in the Cadence driver. I think it won't cause
>>>> any problems. Specifically as follows:
>>>>
>>>> https://lore.kernel.org/linux-pci/5823faec-d972-4c77-90ec-a215c686e0a8@163.com/
>>>> """
>>>> As per PCIe r7.0, sec 7.5.1.1.11, Since all PCI Express Functions are
>>>> required to implement the PCI Express Capability structure, which
>>>> must be included somewhere in this linked list.
>>>> """
>>>>
>>>>
>>>>
>>>> Bjorn also responded as follows:
>>>> https://lore.kernel.org/linux-pci/20260505212306.GA744158@bhelgaas/
>>>> """
>>>> It's true that all Root Ports must have a PCIe Capability.
>>>> """
>>>>
>>>
>>> Ok, what about reading the DBI registers very early?
>>
>> Hi Mani,
>>
>> Yes. I have performed the DBI read register operation at the very beginning
>> of the following code.
>>
>>
>> dw_pcie_ep_init()
>> dw_pcie_get_pcie_cap(pci);
>>
>> dw_pcie_host_init
>> dw_pcie_get_pcie_cap(pci);
>>
>
> These both calls will cause crash on a lot of platforms because these will be
> reading the DBI registers while the resources are not enabled.
Hi Mani,
Next, I will check all the DBI register-related issues. It will be fixed
in the next version. Thank you very much.
Best regards,
Hans
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prev parent reply other threads:[~2026-05-19 16:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-09 13:51 Hans Zhang
2026-05-09 13:51 ` [PATCH 1/3] PCI: dwc: Add pcie_cap field and helper in designware header Hans Zhang
2026-05-09 13:51 ` [PATCH 2/3] PCI: dwc: Use cached PCIe capability offset in core Hans Zhang
2026-05-09 13:51 ` [PATCH 3/3] PCI: dwc: Simplify platform drivers using cached capability offset Hans Zhang
2026-05-19 13:57 ` [PATCH 0/3] PCI: dwc: Cache PCIe capability offset and simplify drivers Manivannan Sadhasivam
2026-05-19 16:09 ` Hans Zhang
2026-05-19 16:15 ` Manivannan Sadhasivam
2026-05-19 16:27 ` Hans Zhang
2026-05-19 16:49 ` Manivannan Sadhasivam
2026-05-19 16:52 ` Hans Zhang [this message]
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