From: Razmik Karapetyan <Razmik.Karapetyan@synopsys.com>
To: John Youn <John.Youn@synopsys.com>,
Felipe Balbi <balbi@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
<linux-usb@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Razmik Karapetyan <Razmik.Karapetyan@synopsys.com>
Subject: [PATCH 1/3] usb: dwc2: Define PCGCCTL1 register in hw.h
Date: Wed, 19 Apr 2017 14:48:56 +0400 [thread overview]
Message-ID: <0bbdaddc-e4f4-4b29-9dfe-d4a21d572ed2@US01WEHTC2.internal.synopsys.com> (raw)
PCGCCTL1 (Power and Clock Control) register will be used
for controlling the core`s active clock gating feature.
Signed-off-by: Razmik Karapetyan <razmik@synopsys.com>
---
drivers/usb/dwc2/hw.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 4592012..b726701 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -643,6 +643,10 @@
#define PCGCTL_GATEHCLK BIT(1)
#define PCGCTL_STOPPCLK BIT(0)
+#define PCGCCTL1 HSOTG_REG(0xe04)
+#define PCGCCTL1_TIMER (0x3 << 1)
+#define PCGCCTL1_GATEEN BIT(0)
+
#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
/* Host Mode Registers */
--
2.7.4
reply other threads:[~2017-04-19 10:49 UTC|newest]
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