* [net-next v2 0/3] bnge changes for RoCE driver
@ 2026-10-06 16:12 Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 1/3] bnge: Add infrastructure support for RoCE MPC channels Siva Reddy Kallam
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Siva Reddy Kallam @ 2026-10-06 16:12 UTC (permalink / raw)
To: leonro, jgg, davem, edumazet, kuba, pabeni, andrew+netdev, horms
Cc: vikas.gupta, ajit.khaparde, netdev, linux-kernel, linux-rdma,
Siva Reddy Kallam
Add bnge specific changes needed for RoCE MPC channel
support.
v1->v2:
- Created pull request for RoCE MPC channel changes
of bnge driver
- Addressed Shasiko review comments
The following are changes since
commit 2c3418fffa9d ("Merge tag 'keys-v7.3-rc7' of
git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd")
Merge tag 'for_linus' in Linus's tree
and are available in the git repository at:
https://github.com/siva-kallam/linux bnge-roce-v2
for you to fetch changes up to
commit 4f4b78c1e577 ("bnge: reserve TX/completion rings for the
RoCE MPC channel")
Sachin Holla (1):
bnge: reserve TX/completion rings for the RoCE MPC channel
Saswati Das (2):
bnge: Add infrastructure support for RoCE MPC channels
bnge: Update HSI
.../net/ethernet/broadcom/bnge/bnge_auxr.c | 1 +
.../net/ethernet/broadcom/bnge/bnge_auxr.h | 1 +
.../net/ethernet/broadcom/bnge/bnge_resc.c | 32 +++-
include/linux/bnge/hsi.h | 161 ++++++++++++++++++
4 files changed, 191 insertions(+), 4 deletions(-)
--
2.43.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* [net-next v2 1/3] bnge: Add infrastructure support for RoCE MPC channels
2026-10-06 16:12 [net-next v2 0/3] bnge changes for RoCE driver Siva Reddy Kallam
@ 2026-10-06 16:12 ` Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 2/3] bnge: Update HSI Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 3/3] bnge: reserve TX/completion rings for the RoCE MPC channel Siva Reddy Kallam
2 siblings, 0 replies; 4+ messages in thread
From: Siva Reddy Kallam @ 2026-10-06 16:12 UTC (permalink / raw)
To: leonro, jgg, davem, edumazet, kuba, pabeni, andrew+netdev, horms
Cc: vikas.gupta, ajit.khaparde, netdev, linux-kernel, linux-rdma,
Saswati Das, Siva Reddy Kallam, Dharmender Garg
From: Saswati Das <saswati.das@broadcom.com>
Add the initial L2 driver plumbing for RoCE MPC (PRIMATE channel)
support:
- Plumb BAR1 through to the RoCE auxiliary device info, alongside the
existing BAR0, so the RoCE driver can reach the doorbell BAR.
This will be used by follow-on patches to issue RoCE commands over the
MPC channels to the firmware.
Signed-off-by: Saswati Das <saswati.das@broadcom.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
Reviewed-by: Dharmender Garg <dharmender.garg@broadcom.com>
---
drivers/net/ethernet/broadcom/bnge/bnge_auxr.c | 1 +
drivers/net/ethernet/broadcom/bnge/bnge_auxr.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_auxr.c b/drivers/net/ethernet/broadcom/bnge/bnge_auxr.c
index 0955b488b6fe..87ae40eab592 100644
--- a/drivers/net/ethernet/broadcom/bnge/bnge_auxr.c
+++ b/drivers/net/ethernet/broadcom/bnge/bnge_auxr.c
@@ -181,6 +181,7 @@ static void bnge_set_auxr_dev_info(struct bnge_auxr_dev *auxr_dev,
auxr_dev->pf_port_id = bd->pf.port_id;
auxr_dev->en_state = bd->state;
auxr_dev->bar0 = bd->bar0;
+ auxr_dev->bar1 = bd->bar1;
}
void bnge_rdma_aux_device_add(struct bnge_dev *bd)
diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_auxr.h b/drivers/net/ethernet/broadcom/bnge/bnge_auxr.h
index 6c5c15ef2b0a..13cb9289f5b8 100644
--- a/drivers/net/ethernet/broadcom/bnge/bnge_auxr.h
+++ b/drivers/net/ethernet/broadcom/bnge/bnge_auxr.h
@@ -46,6 +46,7 @@ struct bnge_auxr_dev {
struct net_device *net;
struct pci_dev *pdev;
void __iomem *bar0;
+ void __iomem *bar1;
struct bnge_msix_info msix_info[BNGE_MAX_ROCE_MSIX];
--
2.43.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* [net-next v2 2/3] bnge: Update HSI
2026-10-06 16:12 [net-next v2 0/3] bnge changes for RoCE driver Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 1/3] bnge: Add infrastructure support for RoCE MPC channels Siva Reddy Kallam
@ 2026-10-06 16:12 ` Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 3/3] bnge: reserve TX/completion rings for the RoCE MPC channel Siva Reddy Kallam
2 siblings, 0 replies; 4+ messages in thread
From: Siva Reddy Kallam @ 2026-10-06 16:12 UTC (permalink / raw)
To: leonro, jgg, davem, edumazet, kuba, pabeni, andrew+netdev, horms
Cc: vikas.gupta, ajit.khaparde, netdev, linux-kernel, linux-rdma,
Saswati Das, Siva Reddy Kallam, Dharmender Garg
From: Saswati Das <saswati.das@broadcom.com>
Add support for 64-bit doorbells and Mid Path Channel (MPC) firmware
commands/completions.
Signed-off-by: Saswati Das <saswati.das@broadcom.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
Reviewed-by: Dharmender Garg <dharmender.garg@broadcom.com>
Reviewed-by: Vikas Gupta <vikas.gupta@broadcom.com>
---
include/linux/bnge/hsi.h | 161 +++++++++++++++++++++++++++++++++++++++
1 file changed, 161 insertions(+)
diff --git a/include/linux/bnge/hsi.h b/include/linux/bnge/hsi.h
index 1f7bd96415a5..a3383f2c7381 100644
--- a/include/linux/bnge/hsi.h
+++ b/include/linux/bnge/hsi.h
@@ -12510,6 +12510,43 @@ struct dbc_dbc {
#define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
};
+/* dbc_dbc64 (size:64b/8B) */
+struct dbc_dbc64 {
+ __le64 dbc;
+ #define DBC_DBC64_INDEX_MASK 0xffffffUL
+ #define DBC_DBC64_INDEX_SFT 0
+ #define DBC_DBC64_EPOCH 0x1000000UL
+ #define DBC_DBC64_TOGGLE_MASK 0x6000000UL
+ #define DBC_DBC64_TOGGLE_SFT 25
+ #define DBC_DBC64_XID_MASK 0xfffff00000000ULL
+ #define DBC_DBC64_XID_SFT 32
+ #define DBC_DBC64_PATH_MASK 0x300000000000000ULL
+ #define DBC_DBC64_PATH_SFT 56
+ #define DBC_DBC64_PATH_ROCE (0x0ULL << 56)
+ #define DBC_DBC64_PATH_L2 (0x1ULL << 56)
+ #define DBC_DBC64_PATH_ENGINE (0x2ULL << 56)
+ #define DBC_DBC64_PATH_LAST DBC_DBC64_PATH_ENGINE
+ #define DBC_DBC64_VALID 0x400000000000000ULL
+ #define DBC_DBC64_DEBUG_TRACE 0x800000000000000ULL
+ #define DBC_DBC64_TYPE_MASK 0xf000000000000000ULL
+ #define DBC_DBC64_TYPE_SFT 60
+ #define DBC_DBC64_TYPE_SQ (0x0ULL << 60)
+ #define DBC_DBC64_TYPE_RQ (0x1ULL << 60)
+ #define DBC_DBC64_TYPE_SRQ (0x2ULL << 60)
+ #define DBC_DBC64_TYPE_SRQ_ARM (0x3ULL << 60)
+ #define DBC_DBC64_TYPE_CQ (0x4ULL << 60)
+ #define DBC_DBC64_TYPE_CQ_ARMSE (0x5ULL << 60)
+ #define DBC_DBC64_TYPE_CQ_ARMALL (0x6ULL << 60)
+ #define DBC_DBC64_TYPE_CQ_ARMENA (0x7ULL << 60)
+ #define DBC_DBC64_TYPE_SRQ_ARMENA (0x8ULL << 60)
+ #define DBC_DBC64_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
+ #define DBC_DBC64_TYPE_NQ (0xaULL << 60)
+ #define DBC_DBC64_TYPE_NQ_ARM (0xbULL << 60)
+ #define DBC_DBC64_TYPE_NQ_MASK (0xeULL << 60)
+ #define DBC_DBC64_TYPE_NULL (0xfULL << 60)
+ #define DBC_DBC64_TYPE_LAST DBC_DBC64_TYPE_NULL
+};
+
/* db_push_start (size:64b/8B) */
struct db_push_start {
u64 db;
@@ -12605,4 +12642,128 @@ struct hcomm_status {
#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
+/* MPC macros */
+#define MPC_CMD_HDR_REQ_TYPE_ICA 0x1UL
+#define MPC_CMD_HDR_REQ_TYPE_RCA 0x2UL
+#define MPC_CMD_HDR_REQ_TYPE_PFVF 0x3UL
+#define MPC_CMD_HDR_REQ_TYPE_EVENT 0x4UL
+#define MPC_CMD_HDR_REQ_TYPE_LAST MPC_CMD_HDR_REQ_TYPE_EVENT
+
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_ENABLE 0x0UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_SA_INIT 0x1UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_NEW_RX_ASSOC 0x2UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_KEY_ROTATE 0x3UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_SA_INIT 0x4UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_KEY_ROTATE 0x5UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_CM_PSP_KEY_SET 0x6UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_INFO_GET 0x7UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_STATS_GET 0x8UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_STATS_CLEAR 0x9UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SA_RX_MATCH_RULE_SET 0xaUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_ICA_SM_PSP_SA_SET 0xbUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY 0x0UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY 0x1UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_CMPL 0x2UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_CMPL 0x3UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_BATCH 0x4UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_BATCH 0x5UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_QP_MODIFY_BATCH_CMPL 0x6UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_AH_MODIFY_BATCH_CMPL 0x7UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_MPC_TEST_CMD 0xc8UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_RCA_MPC_TEST_CMPL 0xc9UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_EVENT_RESP_CMPL 0x0UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE 0x0UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE 0x1UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY 0x2UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY 0x3UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY 0x4UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY 0x5UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_CMPL 0xaUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_CMPL 0xbUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_CMPL 0xcUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_CMPL 0xdUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_CMPL 0xeUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_CMPL 0xfUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_FWD_REQ 0x14UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_FWD_REQ 0x15UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_FWD_REQ 0x16UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_FWD_REQ 0x17UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_FWD_REQ 0x18UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_FWD_REQ 0x19UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_FWD_RESP 0x1eUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_FWD_RESP 0x1fUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_FWD_RESP 0x20UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_FWD_RESP 0x21UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_FWD_RESP 0x22UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_FWD_RESP 0x23UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_ALL_FWD_RESP_CMPL 0x28UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH 0x32UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH 0x33UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH 0x34UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH 0x35UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH 0x36UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH 0x37UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_CMPL 0x3cUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_CMPL 0x3dUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_CMPL 0x3eUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_CMPL 0x3fUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_CMPL 0x40UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_CMPL 0x41UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_FWD_REQ 0x46UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_FWD_REQ 0x47UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_FWD_REQ 0x48UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_FWD_REQ 0x49UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_FWD_REQ 0x4aUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_FWD_REQ 0x4bUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_CREATE_BATCH_FWD_RESP 0x50UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_CREATE_BATCH_FWD_RESP 0x51UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_MODIFY_BATCH_FWD_RESP 0x52UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_MODIFY_BATCH_FWD_RESP 0x53UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_QP_DESTROY_BATCH_FWD_RESP 0x54UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_AH_DESTROY_BATCH_FWD_RESP 0x55UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_ALL_BATCH_FWD_RESP_CMPL 0x5aUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_RGTR 0x64UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_RGTR_CMPL 0x65UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_UNRGTR 0x66UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_DRV_UNRGTR_CMPL 0x67UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_RGTR 0x68UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_RGTR_CMPL 0x69UL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_UNRGTR 0x6aUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_BUF_UNRGTR_CMPL 0x6bUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_CMD 0xcaUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_CMPL 0xcbUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_CMD 0xccUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_CMPL 0xcdUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_REQ 0xceUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_RESP 0xcfUL
+#define MPC_CMD_HDR_REQ_SUB_TYPE_LAST MPC_CMD_HDR_REQ_SUB_TYPE_PFVF_MPC_TEST_FWD_RESP
+
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_NONE 0x0UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_TARGET_ID 0x1UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_SA_NOT_INIT_ENABLED 0x2UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_HW_CMD_FAILED 0x3UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_PSP_MODE 0x4UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_BAD_SPI 0x5UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_SPI_THRESHOLD_BREACHED 0x6UL
+#define MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_ACTIVE_QPS_EXIST 0x7UL
+#define MPC_CMPL_HDR_ERROR_CODE_LAST MPC_CMPL_HDR_ERROR_CODE_ICA_ERR_ACTIVE_QPS_EXIST
+
+/* mpc_cmpl_hdr (size:64b/8B) */
+struct mpc_cmpl_hdr {
+ u8 cmpl_type_reserved;
+ #define CMPL_TYPE_RESERVED_CMPL_TYPE_MASK 0x3fUL
+ #define CMPL_TYPE_RESERVED_CMPL_TYPE_SFT 0
+ #define CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_SHORT 0x1eUL
+ #define CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_LONG 0x1fUL
+ #define CMPL_TYPE_RESERVED_CMPL_TYPE_LAST CMPL_TYPE_RESERVED_CMPL_TYPE_MPC_CMP_LONG
+ u8 error_code_mp_client;
+ #define ERROR_CODE_MP_CLIENT_ERROR_CODE_MASK 0xfUL
+ #define ERROR_CODE_MP_CLIENT_ERROR_CODE_SFT 0
+ #define ERROR_CODE_MP_CLIENT_MP_CLIENT_MASK 0xf0UL
+ #define ERROR_CODE_MP_CLIENT_MP_CLIENT_SFT 4
+ u8 req_type;
+ u8 req_subtype;
+ __le32 opaque;
+};
+
#endif /* _BNGE_HSI_H_ */
--
2.43.5
^ permalink raw reply [flat|nested] 4+ messages in thread
* [net-next v2 3/3] bnge: reserve TX/completion rings for the RoCE MPC channel
2026-10-06 16:12 [net-next v2 0/3] bnge changes for RoCE driver Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 1/3] bnge: Add infrastructure support for RoCE MPC channels Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 2/3] bnge: Update HSI Siva Reddy Kallam
@ 2026-10-06 16:12 ` Siva Reddy Kallam
2 siblings, 0 replies; 4+ messages in thread
From: Siva Reddy Kallam @ 2026-10-06 16:12 UTC (permalink / raw)
To: leonro, jgg, davem, edumazet, kuba, pabeni, andrew+netdev, horms
Cc: vikas.gupta, ajit.khaparde, netdev, linux-kernel, linux-rdma,
Sachin Holla, Siva Reddy Kallam, Dharmender Garg
From: Sachin Holla <sachin.holla@broadcom.com>
When RoCE is enabled, the bng_re driver allocates its own TX/CQ rings
for the MPC control channel out of the same per-function FW ring pool.
Enhanced bnge_reserve_rings() to account for this extra ring count to
avoid pool overflow while allocating netdev rings.
Signed-off-by: Sachin Holla <sachin.holla@broadcom.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
Reviewed-by: Dharmender Garg <dharmender.garg@broadcom.com>
---
.../net/ethernet/broadcom/bnge/bnge_resc.c | 32 ++++++++++++++++---
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c b/drivers/net/ethernet/broadcom/bnge/bnge_resc.c
index 4711dd4945ff..9dfb22b7c7c7 100644
--- a/drivers/net/ethernet/broadcom/bnge/bnge_resc.c
+++ b/drivers/net/ethernet/broadcom/bnge/bnge_resc.c
@@ -110,9 +110,24 @@ static u16 bnge_nqs_demand(struct bnge_dev *bd)
return bd->nq_nr_rings + bnge_aux_get_msix(bd);
}
+static u16 bnge_tx_rings_demand(struct bnge_dev *bd)
+{
+ u16 tx_rings = bd->tx_nr_rings;
+
+ if (bnge_is_roce_en(bd))
+ tx_rings += 1; /* For MPC TX ring */
+
+ return tx_rings;
+}
+
static u16 bnge_cprs_demand(struct bnge_dev *bd)
{
- return bd->tx_nr_rings + bd->rx_nr_rings;
+ u16 cprs = bd->tx_nr_rings + bd->rx_nr_rings;
+
+ if (bnge_is_roce_en(bd))
+ cprs += 1; /* For MPC CQ ring */
+
+ return cprs;
}
static u16 bnge_get_avail_msix(struct bnge_dev *bd, int num)
@@ -250,7 +265,7 @@ static bool bnge_need_reserve_rings(struct bnge_dev *bd)
u16 nqs = bnge_nqs_demand(bd);
u16 vnic;
- if (hw_resc->resv_tx_rings != bd->tx_nr_rings)
+ if (hw_resc->resv_tx_rings != bnge_tx_rings_demand(bd))
return true;
vnic = bnge_get_total_vnics(bd, rx);
@@ -275,6 +290,7 @@ int bnge_reserve_rings(struct bnge_dev *bd)
u16 nq = bd->nq_nr_rings;
u16 aux_msix = 0;
bool sh = false;
+ u16 tx_demand;
u16 tx_cp;
int rc;
@@ -293,11 +309,12 @@ int bnge_reserve_rings(struct bnge_dev *bd)
hwr.nq = bnge_nqs_demand(bd);
}
- hwr.tx = bd->tx_nr_rings;
+ tx_demand = bnge_tx_rings_demand(bd);
+ hwr.tx = tx_demand;
hwr.rx = bd->rx_nr_rings;
if (bd->flags & BNGE_EN_SHARED_CHNL)
sh = true;
- hwr.cmpl = hwr.rx + hwr.tx;
+ hwr.cmpl = bnge_cprs_demand(bd);
hwr.vnic = bnge_get_total_vnics(bd, hwr.rx);
@@ -327,6 +344,13 @@ int bnge_reserve_rings(struct bnge_dev *bd)
if (hwr.stat > bnge_aux_get_stat_ctxs(bd))
hwr.stat -= bnge_aux_get_stat_ctxs(bd);
hwr.nq = min_t(u16, hwr.nq, hwr.stat);
+ /* Drop MPC TX ring from L2 TX ring count; it is owned by RoCE driver */
+ if (bnge_is_roce_en(bd)) {
+ if (hwr.tx >= tx_demand)
+ hwr.tx -= 1;
+ else
+ return -ENOMEM;
+ }
/* Adjust the rings */
rc = bnge_adjust_rings(bd, &rx_rings, &hwr.tx, hwr.nq, sh);
--
2.43.5
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-10-06 16:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2026-10-06 16:12 [net-next v2 0/3] bnge changes for RoCE driver Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 1/3] bnge: Add infrastructure support for RoCE MPC channels Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 2/3] bnge: Update HSI Siva Reddy Kallam
2026-10-06 16:12 ` [net-next v2 3/3] bnge: reserve TX/completion rings for the RoCE MPC channel Siva Reddy Kallam
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