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From: "Jürgen Groß" <jgross@suse.com>
To: Shreshth Srivastava <shreshth.srivastava@intel.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org,
	virtualization@lists.linux.dev
Cc: tglx@kernel.org, mingo@redhat.com, bp@alien8.de,
	dave.hansen@linux.intel.com, hpa@zytor.com,
	ajay.kaher@broadcom.com, alexey.makhalov@broadcom.com,
	bcm-kernel-feedback-list@broadcom.com
Subject: Re: [PATCH v5 04/17] x86/msr: Move MSR trace calls one function level up
Date: Fri, 25 Sep 2026 15:15:05 +0200	[thread overview]
Message-ID: <d322debd-15a5-4dd8-9e34-f69dbecc1099@suse.com> (raw)
In-Reply-To: <20260923202654.1412087-1-shreshth.srivastava@intel.com>


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On 23.09.26 22:26, Shreshth Srivastava wrote:
> On 11.09.26 10:41, Juergen Gross wrote:
>> In order to prepare paravirt inlining of the MSR access instructions
>> move the calls of MSR trace functions one function level up.
>> Introduce {read|write}_msr[_safe]() helpers allowing to have common
>> definitions in msr.h doing the trace calls.
> 
> Hi Juergen,
> 
> read_msr() and write_msr() get a single wrapper below the
> CONFIG_PARAVIRT_XXL ifdef holding the tracepoint, so it fires for either
> implementation. rdpmc() moved into the same ifdef but kept the old
> arrangement: still defined twice, once per arm, with do_trace_rdpmc()
> still called from native_read_pmc() above the ifdef.
> 
> With CONFIG_PARAVIRT_XXL=y that leaves rdpmc() on a path with no trace
> call:
> 
>    rdpmc()                 => paravirt-msr.h, PVOP_CALL1(pv_ops_msr,
>                               read_pmc)
>      xen_read_pmc()        => Xen PV sets pv_ops_msr.read_pmc to this
>        reads the value out of the Xen shared PMU page
>                            => returns without ever calling
>                               native_read_pmc(), which is where
>                               do_trace_rdpmc() sits
> 
> So msr:rdpmc doesn't fire under Xen PV, while msr:read_msr and
> msr:write_msr now do.
> 
> Was that deliberate? If it wasn't, here is a diff that treats rdpmc the
> same way as the other six: rename both definitions to read_pmc(), matching
> the pv_ops_msr member they dispatch to, and add one rdpmc() below the
> endif holding the tracepoint. native_read_pmc() is then an untraced
> primitive next to native_rdmsrq() and native_wrmsrq(). Would something
> like this help?

My patch doesn't change anything in this regard, as the Xen PV case didn't
write trace entries for read_pmc() before.

OTOH I agree that this is more like an oversight than a design decision,
so I'll do something along the lines you are suggesting below.

Thanks for the review!

> 
> diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
> index eba325ecfe4c..6f50b703fba9 100644
> --- a/arch/x86/include/asm/msr.h
> +++ b/arch/x86/include/asm/msr.h
> @@ -305,8 +305,7 @@ static __always_inline u64 native_read_pmc(int counter)
>   	EAX_EDX_DECLARE_ARGS(val, low, high);
>   
>   	asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
> -	if (tracepoint_enabled(rdpmc))
> -		do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
> +
>   	return EAX_EDX_VAL(val, low, high);
>   }
>   
> @@ -343,7 +342,7 @@ static __always_inline int write_msrns_safe(u32 msr, u64 val)
>   	return native_wrmsrns_safe(msr, val);
>   }
>   
> -static __always_inline u64 rdpmc(int counter)
> +static __always_inline u64 read_pmc(int counter)
>   {
>   	return native_read_pmc(counter);
>   }
> @@ -413,6 +412,16 @@ static __always_inline int wrmsrns_safe(u32 msr, u64 val)
>   	return err;
>   }
>   
> +static __always_inline u64 rdpmc(int counter)
> +{
> +	u64 val = read_pmc(counter);
> +
> +	if (tracepoint_enabled(rdpmc))
> +		do_trace_rdpmc(counter, val, 0);
> +
> +	return val;
> +}
> +
>   static __always_inline void sync_cpu_after_wrmsrns(void)
>   {
>   	if (cpu_feature_enabled(X86_FEATURE_WRMSRNS))
> diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/paravirt-msr.h
> index ba3ee64446db..47220bf16cf3 100644
> --- a/arch/x86/include/asm/paravirt-msr.h
> +++ b/arch/x86/include/asm/paravirt-msr.h
> @@ -172,7 +172,7 @@ static __always_inline int write_msrns_safe(u32 msr, u64 val)
>   	return err ? -EIO : 0;
>   }
>   
> -static __always_inline u64 rdpmc(int counter)
> +static __always_inline u64 read_pmc(int counter)
>   {
>   	return PVOP_CALL1(u64, pv_ops_msr, read_pmc, counter);
>   }
> 
> 
> I have no Xen PV guest, so that path is untested. What I did check is that
> the __tracepoint_rdpmc relocation shows up in arch/x86/events/core.o with
> CONFIG_PARAVIRT_XXL=y, where it previously did not, and that x86_64
> defconfig still builds clean with gcc and clang.


Juergen

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  reply	other threads:[~2026-09-25 13:15 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-11  8:41 [PATCH v5 00/17] x86/msr: Inline rdmsr/wrmsr instructions Juergen Gross
2026-09-11  8:41 ` [PATCH v5 01/17] x86/alternative: Support alt_replace_call() with instructions after call Juergen Gross
2026-09-11  8:41 ` [PATCH v5 02/17] coco/tdx: Rename MSR access helpers Juergen Gross
2026-09-11  8:41 ` [PATCH v5 03/17] x86/msr: Minimize usage of native_*() msr access functions Juergen Gross
2026-09-11  8:41 ` [PATCH v5 04/17] x86/msr: Move MSR trace calls one function level up Juergen Gross
2026-09-23 20:26   ` Shreshth Srivastava
2026-09-25 13:15     ` Jürgen Groß [this message]
2026-09-11  8:41 ` [PATCH v5 05/17] x86/hyperv: Switch from __rdmsr() to native_rdmsrq() Juergen Gross
2026-09-11  8:42 ` [PATCH v5 06/17] x86/opcode: Add immediate form MSR instructions Juergen Gross
2026-09-11  8:42 ` [PATCH v5 07/17] x86/extable: Add support for " Juergen Gross
2026-09-11  8:42 ` [PATCH v5 08/17] x86/msr: Make wrmsrns() a first class citizen Juergen Gross
2026-09-11  8:42 ` [PATCH v5 09/17] x86/msr: Introduce sync_cpu_after_wrmsrns() Juergen Gross
2026-09-11  8:42 ` [PATCH v5 10/17] x86/msr: Use the alternatives mechanism for RDMSR Juergen Gross
2026-09-11  8:42 ` [PATCH v5 11/17] x86/alternatives: Add ALTERNATIVE_4() Juergen Gross
2026-09-11  8:42 ` [PATCH v5 12/17] x86/paravirt: Split off MSR related hooks into new header Juergen Gross
2026-09-11  8:42 ` [PATCH v5 13/17] x86/paravirt: Prepare support of MSR instruction interfaces Juergen Gross
2026-09-11  8:42 ` [PATCH v5 14/17] x86/paravirt: Switch MSR access pv_ops functions to " Juergen Gross
2026-09-11  8:42 ` [PATCH v5 15/17] x86/msr: Reduce number of low level MSR access helpers Juergen Gross
2026-09-11  8:42 ` [PATCH v5 16/17] x86/paravirt: Use alternatives for MSR access with paravirt Juergen Gross
2026-09-11  8:42 ` [PATCH v5 17/17] x86/msr: Make all MSR access functions __always_inline Juergen Gross
2026-09-23 19:36 ` [PATCH v5 00/17] x86/msr: Inline rdmsr/wrmsr instructions Shreshth Srivastava
2026-09-23 20:15   ` Nick Desaulniers
2026-09-25 10:25   ` Jürgen Groß

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