From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Jingoo Han <jingoohan1@gmail.com>,
Manivannan Sadhasivam <mani@kernel.org>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
"Krzysztof Wilczynski" <kwilczynski@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Vidya Sagar <vidyas@nvidia.com>,
Niklas Cassel <cassel@kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 1/5] PCI: dwc: Add RAS event counter field masks
Date: Wed, 23 Sep 2026 12:47:02 +0530 [thread overview]
Message-ID: <20260923071706.1134320-2-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20260923071706.1134320-1-mmaddireddy@nvidia.com>
Add complete bit masks for the DesignWare RAS-DES event counter
fields so consumers can use FIELD_PREP() and FIELD_MODIFY() without
open-coded shifts.
Keep the existing shift-based definitions for now so current users
keep building until their call sites are converted.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0735ae940924..c4db241547be 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -278,14 +278,17 @@
#define EVENT_COUNTER_ALL_CLEAR 0x3
#define EVENT_COUNTER_ENABLE_ALL 0x7
#define EVENT_COUNTER_ENABLE_SHIFT 2
+#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
+#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16)
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
#define EVENT_COUNTER_EVENT_L1_1 0x7
#define EVENT_COUNTER_EVENT_L1_2 0x8
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
+#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24)
#define EVENT_COUNTER_GROUP_5 0x5
#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc
--
2.34.1
next prev parent reply other threads:[~2026-09-23 7:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` Manikanta Maddireddy [this message]
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
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