* [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling
@ 2026-09-23 7:17 Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
This series addresses review feedback around register field handling in the
DWC PCIe code and the Tegra194 PCIe driver.
The first patches add shared masks for the RAS-DES event counter fields,
convert Tegra194 register programming to FIELD_PREP()/FIELD_MODIFY(), and
drop shift macros that become unused after the conversion. The final
patches make Tegra194 use the common RAS-DES selector definitions and
consolidate the event counter field definitions in the DWC header.
There should be no functional change intended beyond making the
bitfield programming explicit and keeping the shared RAS-DES definitions in
one place.
Manikanta Maddireddy (5):
PCI: dwc: Add RAS event counter field masks
PCI: tegra194: Use FIELD_*() for register fields
PCI: dwc: Drop unused shift macros
PCI: tegra194: Use standard RAS event selector mask
PCI: dwc: Consolidate RAS-DES event counter fields
.../controller/dwc/pcie-designware-debugfs.c | 56 ++++---
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
drivers/pci/controller/dwc/pcie-tegra194.c | 145 +++++++++---------
3 files changed, 106 insertions(+), 105 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/5] PCI: dwc: Add RAS event counter field masks
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
@ 2026-09-23 7:17 ` Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
Add complete bit masks for the DesignWare RAS-DES event counter
fields so consumers can use FIELD_PREP() and FIELD_MODIFY() without
open-coded shifts.
Keep the existing shift-based definitions for now so current users
keep building until their call sites are converted.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0735ae940924..c4db241547be 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -278,14 +278,17 @@
#define EVENT_COUNTER_ALL_CLEAR 0x3
#define EVENT_COUNTER_ENABLE_ALL 0x7
#define EVENT_COUNTER_ENABLE_SHIFT 2
+#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
+#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16)
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
#define EVENT_COUNTER_EVENT_L1_1 0x7
#define EVENT_COUNTER_EVENT_L1_2 0x8
#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
+#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24)
#define EVENT_COUNTER_GROUP_5 0x5
#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
@ 2026-09-23 7:17 ` Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
Several Tegra194 APPL and DesignWare register fields are programmed
with open-coded shifts, which makes the register programming more
verbose than necessary.
Use FIELD_PREP(), FIELD_MODIFY() and FIELD_GET() at the Tegra call
sites where values are shifted into fields. The LTSSM state constants
are converted from pre-shifted register values to unshifted field
values for FIELD_GET().
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20260515070753.3852840-2-mmaddireddy@nvidia.com
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 145 ++++++++++-----------
1 file changed, 71 insertions(+), 74 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 63a0f56cad8e..3cfb386dd433 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -50,8 +50,7 @@
#define APPL_CTRL_SYS_PRE_DET_STATE BIT(6)
#define APPL_CTRL_LTSSM_EN BIT(7)
#define APPL_CTRL_HW_HOT_RST_EN BIT(20)
-#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
-#define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
+#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(23, 22)
#define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
#define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN 0x2
@@ -136,14 +135,13 @@
#define APPL_DEBUG 0xD0
#define APPL_DEBUG_PM_LINKST_IN_L2_LAT BIT(21)
-#define APPL_DEBUG_PM_LINKST_IN_L0 0x11
#define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3)
-#define APPL_DEBUG_LTSSM_STATE_SHIFT 3
-#define LTSSM_STATE_DETECT_QUIET 0x00
-#define LTSSM_STATE_DETECT_ACT 0x08
-#define LTSSM_STATE_PRE_DETECT_QUIET 0x28
-#define LTSSM_STATE_DETECT_WAIT 0x30
-#define LTSSM_STATE_L2_IDLE 0xa8
+#define LTSSM_STATE_DETECT_QUIET 0x0
+#define LTSSM_STATE_DETECT_ACT 0x1
+#define LTSSM_STATE_PRE_DETECT_QUIET 0x5
+#define LTSSM_STATE_DETECT_WAIT 0x6
+#define LTSSM_STATE_L0 0x11
+#define LTSSM_STATE_L2_IDLE 0x15
#define APPL_RADM_STATUS 0xE4
#define APPL_PM_XMT_TURNOFF_STATE BIT(0)
@@ -162,7 +160,6 @@
#define APPL_CFG_MISC 0x110
#define APPL_CFG_MISC_SLV_EP_MODE BIT(14)
#define APPL_CFG_MISC_ARCACHE_MASK GENMASK(13, 10)
-#define APPL_CFG_MISC_ARCACHE_SHIFT 10
#define APPL_CFG_MISC_ARCACHE_VAL 3
#define APPL_CFG_SLCG_OVERRIDE 0x114
@@ -178,14 +175,14 @@
#define CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE BIT(16)
#define CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x718
-#define CFG_TIMER_CTRL_ACK_NAK_SHIFT (19)
+#define CFG_TIMER_CTRL_ACK_NAK_MASK GENMASK(23, 19)
+#define CFG_TIMER_CTRL_ACK_NAK_VAL 1
#define N_FTS_VAL 52
#define FTS_VAL 52
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
-#define AMBA_ERROR_RESPONSE_RRS_SHIFT 3
-#define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(1, 0)
+#define AMBA_ERROR_RESPONSE_RRS_MASK GENMASK(4, 3)
#define AMBA_ERROR_RESPONSE_RRS_OKAY 0
#define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFFFFFF 1
#define AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 2
@@ -202,7 +199,6 @@
#define CAP_SPCIE_CAP_OFF 0x154
#define CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK GENMASK(3, 0)
#define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8)
-#define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8
#define LTSSM_DELAY_US 10000 /* 10 ms */
#define LTSSM_TIMEOUT_US 120000 /* 120 ms */
@@ -348,8 +344,8 @@ static void apply_bad_link_workaround(struct dw_pcie_rp *pp)
dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
PCI_EXP_LNKCTL2);
- val &= ~PCI_EXP_LNKCTL2_TLS;
- val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
+ FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val,
+ PCI_EXP_LNKCTL2_TLS_2_5GT);
dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
PCI_EXP_LNKCTL2, val);
@@ -622,10 +618,9 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
- val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
- val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
- val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
- val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
+ FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_FIELD_MASK, &val, event);
+ FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, EVENT_COUNTER_GROUP_5);
+ FIELD_MODIFY(EVENT_COUNTER_ENABLE_MASK, &val, EVENT_COUNTER_ENABLE_ALL);
dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
@@ -661,8 +656,8 @@ static int aspm_state_cnt(struct seq_file *s, void *data)
EVENT_COUNTER_ALL_CLEAR);
/* Re-enable counting */
- val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
- val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
+ val = FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_ENABLE_ALL);
+ val |= FIELD_PREP(EVENT_COUNTER_GROUP_SEL_MASK, EVENT_COUNTER_GROUP_5);
dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
@@ -680,16 +675,15 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
PCI_EXT_CAP_ID_VNDR);
/* Enable ASPM counters */
- val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
- val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
+ val = FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, EVENT_COUNTER_ENABLE_ALL);
+ val |= FIELD_PREP(EVENT_COUNTER_GROUP_SEL_MASK, EVENT_COUNTER_GROUP_5);
dw_pcie_writel_dbi(pci, pcie->ras_des_cap +
PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
/* Program T_cmrt and T_pwr_on values */
val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);
- val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
- val |= (pcie->aspm_cmrt << 8);
- val |= (pcie->aspm_pwr_on_t << 19);
+ FIELD_MODIFY(PCI_L1SS_CAP_CM_RESTORE_TIME, &val, pcie->aspm_cmrt);
+ FIELD_MODIFY(PCI_L1SS_CAP_P_PWR_ON_VALUE, &val, pcie->aspm_pwr_on_t);
dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);
if (pcie->supports_clkreq)
@@ -714,10 +708,10 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
/* Program L0s and L1 entrance latencies */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
- val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
- val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
- val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
- val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
+ FIELD_MODIFY(PORT_AFR_L0S_ENTRANCE_LAT_MASK, &val,
+ pcie->aspm_l0s_enter_lat);
+ FIELD_MODIFY(PORT_AFR_L1_ENTRANCE_LAT_MASK, &val,
+ pcie->aspm_l1_enter_lat);
val |= PORT_AFR_ENTER_ASPM;
dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
@@ -851,22 +845,20 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
/* Program init preset */
for (i = 0; i < pcie->num_lanes; i++) {
val = dw_pcie_readw_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2));
- val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
- val |= GEN3_GEN4_EQ_PRESET_INIT;
- val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
- val |= (GEN3_GEN4_EQ_PRESET_INIT <<
- CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
+ FIELD_MODIFY(CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK, &val,
+ GEN3_GEN4_EQ_PRESET_INIT);
+ FIELD_MODIFY(CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK, &val,
+ GEN3_GEN4_EQ_PRESET_INIT);
dw_pcie_writew_dbi(pci, CAP_SPCIE_CAP_OFF + (i * 2), val);
offset = dw_pcie_find_ext_capability(pci,
PCI_EXT_CAP_ID_PL_16GT) +
PCI_PL_16GT_LE_CTRL;
val = dw_pcie_readb_dbi(pci, offset + i);
- val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
- val |= GEN3_GEN4_EQ_PRESET_INIT;
- val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
- val |= (GEN3_GEN4_EQ_PRESET_INIT <<
- PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
+ FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK, &val,
+ GEN3_GEN4_EQ_PRESET_INIT);
+ FIELD_MODIFY(PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK, &val,
+ GEN3_GEN4_EQ_PRESET_INIT);
dw_pcie_writeb_dbi(pci, offset + i, val);
}
@@ -880,8 +872,7 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
- val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
+ FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, &val, 0x1);
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
@@ -921,9 +912,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
/* Enable as 0xFFFF0001 response for RRS */
val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
- val &= ~(AMBA_ERROR_RESPONSE_RRS_MASK << AMBA_ERROR_RESPONSE_RRS_SHIFT);
- val |= (AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001 <<
- AMBA_ERROR_RESPONSE_RRS_SHIFT);
+ FIELD_MODIFY(AMBA_ERROR_RESPONSE_RRS_MASK, &val,
+ AMBA_ERROR_RESPONSE_RRS_OKAY_FFFF0001);
dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
/* Clear Slot Clock Configuration bit if SRNS configuration */
@@ -947,7 +937,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
- val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
+ FIELD_MODIFY(CFG_TIMER_CTRL_ACK_NAK_MASK, &val,
+ CFG_TIMER_CTRL_ACK_NAK_VAL);
dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
}
@@ -1002,11 +993,10 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
* link up once again with DLF disabled.
*/
val = appl_readl(pcie, APPL_DEBUG);
- val &= APPL_DEBUG_LTSSM_STATE_MASK;
- val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
+ val = FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val);
tmp = appl_readl(pcie, APPL_LINK_STATUS);
tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
- if (!(val == 0x11 && !tmp)) {
+ if (!(val == LTSSM_STATE_L0 && !tmp)) {
/* Link is down for all good reasons */
return 0;
}
@@ -1419,10 +1409,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) {
/* Enable HW_HOT_RST mode */
val = appl_readl(pcie, APPL_CTRL);
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
- val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val,
+ APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN);
val |= APPL_CTRL_HW_HOT_RST_EN;
appl_writel(pcie, val, APPL_CTRL);
}
@@ -1446,7 +1434,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
val = appl_readl(pcie, APPL_CFG_MISC);
- val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
+ FIELD_MODIFY(APPL_CFG_MISC_ARCACHE_MASK, &val,
+ APPL_CFG_MISC_ARCACHE_VAL);
appl_writel(pcie, val, APPL_CFG_MISC);
if (pcie->enable_srns || pcie->enable_ext_refclk) {
@@ -1605,10 +1594,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
appl_writel(pcie, data, APPL_PINMUX);
err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,
- ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
- ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
- ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
- ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT),
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) ==
+ LTSSM_STATE_DETECT_QUIET) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) ==
+ LTSSM_STATE_DETECT_ACT) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) ==
+ LTSSM_STATE_PRE_DETECT_QUIET) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, data) ==
+ LTSSM_STATE_DETECT_WAIT),
LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
if (err)
dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", data, err);
@@ -1694,11 +1687,16 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
return;
ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) ||
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) ||
- ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE),
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) ==
+ LTSSM_STATE_DETECT_QUIET) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) ==
+ LTSSM_STATE_DETECT_ACT) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) ==
+ LTSSM_STATE_PRE_DETECT_QUIET) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) ==
+ LTSSM_STATE_DETECT_WAIT) ||
+ (FIELD_GET(APPL_DEBUG_LTSSM_STATE_MASK, val) ==
+ LTSSM_STATE_L2_IDLE),
LTSSM_DELAY_US, LTSSM_TIMEOUT_US);
if (ret)
dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", val, ret);
@@ -1817,13 +1815,14 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val = appl_readl(pcie, APPL_CTRL);
val |= APPL_CTRL_SYS_PRE_DET_STATE;
val |= APPL_CTRL_HW_HOT_RST_EN;
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
- val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val,
+ APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN);
appl_writel(pcie, val, APPL_CTRL);
val = appl_readl(pcie, APPL_CFG_MISC);
val |= APPL_CFG_MISC_SLV_EP_MODE;
- val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
+ FIELD_MODIFY(APPL_CFG_MISC_ARCACHE_MASK, &val,
+ APPL_CFG_MISC_ARCACHE_VAL);
appl_writel(pcie, val, APPL_CFG_MISC);
val = appl_readl(pcie, APPL_PINMUX);
@@ -1875,7 +1874,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
- val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
+ FIELD_MODIFY(CFG_TIMER_CTRL_ACK_NAK_MASK, &val,
+ CFG_TIMER_CTRL_ACK_NAK_VAL);
dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
}
@@ -2390,8 +2390,7 @@ static int tegra_pcie_dw_suspend_late(struct device *dev)
/* Enable HW_HOT_RST mode */
if (!pcie->of_data->has_sbr_reset_fix) {
val = appl_readl(pcie, APPL_CTRL);
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val, 0);
val |= APPL_CTRL_HW_HOT_RST_EN;
appl_writel(pcie, val, APPL_CTRL);
}
@@ -2466,10 +2465,8 @@ static int tegra_pcie_dw_resume_early(struct device *dev)
/* Disable HW_HOT_RST mode */
if (!pcie->of_data->has_sbr_reset_fix) {
val = appl_readl(pcie, APPL_CTRL);
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
- val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
+ FIELD_MODIFY(APPL_CTRL_HW_HOT_RST_MODE_MASK, &val,
+ APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST);
val &= ~APPL_CTRL_HW_HOT_RST_EN;
appl_writel(pcie, val, APPL_CTRL);
}
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/5] PCI: dwc: Drop unused shift macros
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
@ 2026-09-23 7:17 ` Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
4 siblings, 0 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
Tegra no longer uses the DesignWare field shift macros after
converting the call sites to FIELD_PREP() and FIELD_MODIFY().
Remove the unused shift macros and the old narrow event-selector mask.
Add the complete event-selector field with the standard mask name, and
keep a temporary alias so existing users keep building until they are
converted.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index c4db241547be..f70b7da97e07 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -82,9 +82,7 @@
#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
#define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)
#define PORT_AFR_ENTER_ASPM BIT(30)
-#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
-#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
#define PCIE_PORT_LINK_CONTROL 0x710
@@ -151,7 +149,6 @@
#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9)
#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
#define GEN3_EQ_CONTROL_OFF 0x8A8
@@ -277,17 +274,14 @@
#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8
#define EVENT_COUNTER_ALL_CLEAR 0x3
#define EVENT_COUNTER_ENABLE_ALL 0x7
-#define EVENT_COUNTER_ENABLE_SHIFT 2
#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
-#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
-#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
-#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16)
+#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16)
+#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
#define EVENT_COUNTER_EVENT_L1_1 0x7
#define EVENT_COUNTER_EVENT_L1_2 0x8
-#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24)
#define EVENT_COUNTER_GROUP_5 0x5
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
` (2 preceding siblings ...)
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
@ 2026-09-23 7:17 ` Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
4 siblings, 0 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
Use the common DesignWare EVENT_COUNTER_EVENT_SEL_MASK name after the
complete RAS-DES event selector field mask has replaced the old narrow
value mask.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 3cfb386dd433..2462da8664e0 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -618,7 +618,7 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
- FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_FIELD_MASK, &val, event);
+ FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val, event);
FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val, EVENT_COUNTER_GROUP_5);
FIELD_MODIFY(EVENT_COUNTER_ENABLE_MASK, &val, EVENT_COUNTER_ENABLE_ALL);
dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
` (3 preceding siblings ...)
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
@ 2026-09-23 7:17 ` Manikanta Maddireddy
4 siblings, 0 replies; 6+ messages in thread
From: Manikanta Maddireddy @ 2026-09-23 7:17 UTC (permalink / raw)
To: Jingoo Han, Manivannan Sadhasivam, Lorenzo Pieralisi,
Krzysztof Wilczynski, Bjorn Helgaas, linux-pci
Cc: Rob Herring, Thierry Reding, Jonathan Hunter, Vidya Sagar,
Niklas Cassel, linux-kernel, linux-tegra, Manikanta Maddireddy
Use the shared DesignWare RAS-DES event counter register offsets and
field masks in the common debugfs code instead of carrying duplicate
private definitions.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
.../controller/dwc/pcie-designware-debugfs.c | 56 +++++++++++--------
drivers/pci/controller/dwc/pcie-designware.h | 1 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
index be0b84665c9e..daabc6ff0d85 100644
--- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
+++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
@@ -31,14 +31,8 @@
#define ERR_INJ_ENABLE_REG 0x30
-#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc
-
-#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8
-#define EVENT_COUNTER_GROUP_SELECT GENMASK(27, 24)
-#define EVENT_COUNTER_EVENT_SELECT GENMASK(23, 16)
#define EVENT_COUNTER_LANE_SELECT GENMASK(11, 8)
#define EVENT_COUNTER_STATUS BIT(7)
-#define EVENT_COUNTER_ENABLE GENMASK(4, 2)
#define PER_EVENT_ON 0x3
#define PER_EVENT_OFF 0x1
@@ -356,11 +350,15 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,
{
u32 val;
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
- val &= ~EVENT_COUNTER_ENABLE;
- FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);
- FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
+ val &= ~EVENT_COUNTER_ENABLE_MASK;
+ FIELD_MODIFY(EVENT_COUNTER_GROUP_SEL_MASK, &val,
+ event_list[pdata->idx].group_no);
+ FIELD_MODIFY(EVENT_COUNTER_EVENT_SEL_MASK, &val,
+ event_list[pdata->idx].event_no);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
}
static ssize_t counter_enable_read(struct file *file, char __user *buf,
@@ -375,13 +373,16 @@ static ssize_t counter_enable_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
mutex_unlock(&rinfo->reg_event_lock);
val = FIELD_GET(EVENT_COUNTER_STATUS, val);
if (val)
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Enabled\n");
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter Enabled\n");
else
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter Disabled\n");
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter Disabled\n");
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
}
@@ -401,13 +402,15 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
if (enable)
- val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_ON);
+ val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_ON);
else
- val |= FIELD_PREP(EVENT_COUNTER_ENABLE, PER_EVENT_OFF);
+ val |= FIELD_PREP(EVENT_COUNTER_ENABLE_MASK, PER_EVENT_OFF);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
/*
* While enabling the counter, always read the status back to check if
@@ -416,7 +419,7 @@ static ssize_t counter_enable_write(struct file *file, const char __user *buf,
*/
if (enable) {
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
- RAS_DES_EVENT_COUNTER_CTRL_REG);
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
if (!FIELD_GET(EVENT_COUNTER_STATUS, val)) {
mutex_unlock(&rinfo->reg_event_lock);
return -EOPNOTSUPP;
@@ -440,7 +443,8 @@ static ssize_t counter_lane_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
mutex_unlock(&rinfo->reg_event_lock);
val = FIELD_GET(EVENT_COUNTER_LANE_SELECT, val);
pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Lane: %d\n", val);
@@ -463,9 +467,11 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);
- dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
+ dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_CONTROL, val);
mutex_unlock(&rinfo->reg_event_lock);
return count;
@@ -483,9 +489,11 @@ static ssize_t counter_value_read(struct file *file, char __user *buf,
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
- val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_DATA_REG);
+ val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset +
+ PCIE_RAS_DES_EVENT_COUNTER_DATA);
mutex_unlock(&rinfo->reg_event_lock);
- pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX, "Counter value: %d\n", val);
+ pos = scnprintf(debugfs_buf, DWC_DEBUGFS_BUF_MAX,
+ "Counter value: %d\n", val);
return simple_read_from_buffer(buf, count, ppos, debugfs_buf, pos);
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index f70b7da97e07..4d55339750f0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -276,7 +276,6 @@
#define EVENT_COUNTER_ENABLE_ALL 0x7
#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16)
-#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-09-23 7:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-23 7:17 [PATCH 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 3/5] PCI: dwc: Drop unused shift macros Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-09-23 7:17 ` [PATCH 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
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